PIC18F6390 Datasheet, PDF (380/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
FIGURE 26-13: EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
SCK
(CKP = 1)
80
79
SDO
MSb
bit 6 - - - - - - 1
SDI
Note:
75, 76
MSb In
74
73
Refer to Figure 26-4 for load conditions.
bit 6 - - - - 1
83
79
78
LSb
77
LSb In
TABLE 26-15: EXAMPLE SPI™ MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS↓ to SCK↓ or SCK↑ Input
TSSL2SCL
TCY
—
71
TSCH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TSCL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
—
73A TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74
TSCH2DIL, Hold time of SDI data input to SCK edge
TSCL2DIL
100
—
75
TDOR
SDO data output rise time
PIC18FXXXX
—
25
PIC18LFXXXX
—
45
76
TDOF
SDO data output fall time
—
25
77
TSSH2DOZ SS↑ to SDO output hi-impedance
10
50
78
TSCR
SCK output rise time (Master mode) PIC18FXXXX
—
25
PIC18LFXXXX
—
45
79
TSCF
SCK output fall time (Master mode)
—
25
80
TSCH2DOV, SDO data output valid after SCK edge PIC18FXXXX
—
50
TSCL2DOV
PIC18LFXXXX
—
100
83
TSCH2SSH, SS ↑ after SCK edge
TSCL2SSH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns VDD = 2.0V
ns
ns
ns
ns VDD = 2.0V
ns
ns
ns VDD = 2.0V
ns
DS39629B-page 378
Preliminary
 2004 Microchip Technology Inc.