PIC18F6390 Datasheet, PDF (407/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
Timer1 .............................................................................. 135
16-Bit Read/Write Mode ........................................... 137
Associated Registers ............................................... 139
Interrupt .................................................................... 138
Operation ................................................................. 136
Oscillator .......................................................... 135, 137
Layout Considerations ..................................... 138
Overflow Interrupt .................................................... 135
Resetting, Using a Special Event
Trigger Output (CCP) ....................................... 138
TMR1H Register ...................................................... 135
TMR1L Register ....................................................... 135
Use as a Real-Time Clock ....................................... 138
Timer2 .............................................................................. 141
Associated Registers ............................................... 142
Interrupt .................................................................... 142
Operation ................................................................. 141
Output ...................................................................... 142
PR2 Register ............................................................ 153
TMR2 to PR2 Match Interrupt .................................. 153
Timer3 .............................................................................. 143
16-Bit Read/Write Mode ........................................... 145
Associated Registers ............................................... 145
Operation ................................................................. 144
Oscillator .......................................................... 143, 145
Overflow Interrupt ............................................ 143, 145
Special Event Trigger (CCP) .................................... 145
TMR3H Register ...................................................... 143
TMR3L Register ....................................................... 143
Timing Diagrams
A/D Conversion ........................................................ 386
Acknowledge Sequence .......................................... 190
Asynchronous Reception ................................. 209, 225
Asynchronous Transmission ............................ 207, 223
Asynchronous Transmission
(Back to Back) ......................................... 207, 223
Automatic Baud Rate Calculation ............................ 205
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 210
Auto-Wake-up Bit (WUE) During Sleep ................... 210
Baud Rate Generator with Clock Arbitration ............ 184
BRG Overflow Sequence ......................................... 205
BRG Reset Due to SDA Arbitration
During Start Condition ..................................... 193
Brown-out Reset (BOR) ........................................... 373
Bus Collision During a Repeated Start
Condition (Case 1) ........................................... 194
Bus Collision During a Repeated Start
Condition (Case 2) ........................................... 194
Bus Collision During a Start
Condition (SCL = 0) ......................................... 193
Bus Collision During a Start
Condition (SDA Only) ...................................... 192
Bus Collision During a Stop
Condition (Case 1) ........................................... 195
Bus Collision During a Stop
Condition (Case 2) ........................................... 195
Bus Collision for Transmit and Acknowledge ........... 191
Capture/Compare/PWM (All CCP Modules) ............ 375
CLKO and I/O .......................................................... 372
Clock Synchronization ............................................. 177
Clock/Instruction Cycle .............................................. 69
Example SPI Master Mode (CKE = 0) ..................... 376
Example SPI Master Mode (CKE = 1) ..................... 377
Example SPI Slave Mode (CKE = 0) ....................... 378
Example SPI Slave Mode (CKE = 1) ....................... 379
External Clock (All Modes Except PLL) ................... 370
Fail-Safe Clock Monitor ........................................... 291
High/Low-Voltage Detect Characteristics ................ 367
High-Voltage Detect Operation (VDIRMAG = 1) ..... 254
I²C Bus Data ............................................................ 380
I²C Bus Start/Stop Bits ............................................ 380
I²C Master Mode (7 or 10-Bit Transmission) ........... 188
I²C Master Mode (7-Bit Reception) ......................... 189
I²C Master Mode First Start Bit ................................ 185
I²C Slave Mode (10-Bit Reception, SEN = 0) .......... 174
I²C Slave Mode (10-Bit Reception, SEN = 1) .......... 179
I²C Slave Mode (10-Bit Transmission) .................... 175
I²C Slave Mode (7-Bit Reception, SEN = 0) ............ 172
I²C Slave Mode (7-Bit Reception, SEN = 1) ............ 178
I²C Slave Mode (7-Bit Transmission) ...................... 173
I²C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) ............ 180
I²C Stop Condition Receive or
Transmit Mode ................................................. 190
LCD Interrupt Timing in Quarter-Duty
Cycle Drive ...................................................... 276
LCD Sleep Entry/Exit when SLPEN = 1
or CS1:CS0 = 00 ............................................. 277
Low-Voltage Detect Operation
(VDIRMAG = 0) ............................................... 253
Master SSP I²C Bus Data ....................................... 382
Master SSP I²C Bus Start/Stop Bits ........................ 382
PWM Output ............................................................ 153
Repeat Start Condition ............................................ 186
Reset, Watchdog Timer (WDT),
Oscillator Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 373
Send Break Character Sequence ............................ 211
Slave Synchronization ............................................. 163
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 57
SPI Mode (Master Mode) ........................................ 162
SPI Mode (Slave Mode, CKE = 0) ........................... 164
SPI Mode (Slave Mode, CKE = 1) ........................... 164
Synchronous Reception
(Master Mode, SREN) ............................. 214, 228
Synchronous Transmission ............................. 212, 226
Synchronous Transmission
(Through TXEN) ...................................... 213, 227
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) .......................................... 57
Time-out Sequence on Power-up
MCLR Not Tied to VDD, Case 1 ......................... 56
MCLR Not Tied to VDD, Case 2 ......................... 56
MCLR Tied to VDD, VDD Rise < TPWRT ............. 56
Timer0 and Timer1 External Clock .......................... 374
Transition for Entry to PRI_IDLE Mode ..................... 46
Transition for Entry to SEC_RUN Mode .................... 43
Transition for Entry to Sleep Mode ............................ 45
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................ 289
Transition for Wake from Idle to Run Mode ............... 46
Transition for Wake from Sleep (HSPLL) .................. 45
Transition from RC_RUN Mode to
PRI_RUN Mode ................................................. 44
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 43
Transition to RC_RUN Mode ..................................... 44
Type-A in 1/2 Mux, 1/2 Bias Drive ........................... 266
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 405