ISL78226 Datasheet, PDF (92/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Layout Considerations
For DC/DC converter design, the PCB layout is very important to
ensure the desired performance.
1. Place input ceramic capacitors as close as possible to the IC's
VIN and PGND/SGND pins.
2. Place the output ceramic capacitors as close as possible to
the power MOSFET. Keep this loop (output ceramic capacitor
and MOSFETs for each phase) as small as possible to reduce
voltage spikes induced by the trace parasitic inductances
when MOSFETs switching ON and OFF.
3. Place the output aluminum capacitors close to power
MOSFETs too.
4. Keep the phase node copper area small but large enough to
handle the load current.
5. Place the input aluminum and some ceramic capacitors close
to the input inductors and power MOSFETs.
6. Place multiple vias under the thermal pad of the IC. The
thermal pad should be connected to the ground copper plane
with as large an area as possible in multiple layers to
effectively reduce the thermal impedance. Figure 38 shows
the layout example for vias in the IC bottom pad.
recommended. Assuming R_SENx is placed in the top layer
(red), route one current sense connection from the middle of
one R_SENx pad in the top layer under the resistor (red trace).
For the other current sensing trace, from the middle of the
other pad on R_SENx in the top layer, after a short distance, via
down to the second layer and route this trace right under the
top layer current sense trace.
13. Keep the current sensing traces far from the noisy traces like
gate driving traces (LGx, UGx and PHx), phase nodes in power
stage, BOOTx signals, output switching pulse currents, driving
bias traces and input inductor ripple current signals, etc.
In the actual application, sometimes a large ringing noise at the
IPH node and the BOOT node are observed. This noise is caused
by high DV/DT phase node switching, parasitic PH node
capacitance due to PCB routing, and the parasitic inductance. To
reduce this noise, a resistor can be added between the BOOT pin
and the bootstrap capacitor. A large resistor value will reduce the
ringing noise at PH node but limits the charging of the bootstrap
capacitor during the low-side MOSFET on-time, especially when
the controller is operating at a very low duty cycle. Also, a large
resistance causes a voltage dip at the BOOT pin each time the
high-side driver turns on the high-side MOSFET. Make sure that
this voltage dip will not trigger the high-side BOOT to PH UVLO
threshold (3V typical), especially when a large Qg MOSFET is
used.
FIGURE 38. RECOMMENDED LAYOUT PATTERN FOR VIAS IN THE
IC BOTTOM PAD
7. Place the 10µF decoupling ceramic capacitor at the PVCC pin
and as close as possible to the IC. Put multiple vias close to
the ground pad of this capacitor.
8. Place the 1µF decoupling ceramic capacitor at the VCC pin
and as close as possible to the IC. Put multiple vias close to
the ground pad of this capacitor.
9. Keep the bootstrap capacitor as close as possible to the driver
IC.
10. Keep the driver traces as short as possible and with relatively
large width (25 mil to 40 mil is recommended), and avoid
using vias or a minimal number of vias in the driver path to
achieve the lowest impedance.
11. Place the current sense setting resistors and the filter
capacitor (shown as R_SETxB, R_BIASxB, and C_ISENx in Figure 32
on page 37) as close as possible to the IC. Keep each pair of
the traces close to each other to avoid undesired switching
noise injections.
12. The current sensing traces must be laid out very carefully
since they carry tiny signals with only tens of mV.
For the current sensing traces close to the power sense
resistor (R_SENx), the layout pattern shown in Figure 39 is
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FIGURE 39. RECOMMENDED LAYOUT PATTERN FOR CURRENT
SENSE TRACES REGULATOR
FN8887.0
November 7, 2016