ISL78226 Datasheet, PDF (73/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Boot Refresh Interval Setting Bits (0xEC: Bit 2:0)
Sets the interval of boot refresh pulses.
BIT2
BIT1
BIT0
0
0
0
500µS (default)
0
0
1
100µS
0
1
0
200µS
0
1
1
300µS
1
0
0
750µS
1
0
1
1ms
1
1
0
1.5ms
1
1
1
2ms
DESCRIPTION
Boot Refresh Pulse Width Setting Bit (0xEC: Bit 3)
Sets the boot refresh pulse width.
BIT3
0
1/12 of PWM pulse period (default)
1
1/6 of PWM pulse period
DESCRIPTION
Boot Refresh Pulse Count before Soft-Start (0xEC: Bit 4)
Sets the boot refresh pulse count before soft-start.
BIT4
0
8 pulses (default)
1
4 pulses
DESCRIPTION
Phase Drop Enable Blanking Time after Phase-Add (0xEC: Bit 6)
Sets the boot refresh pulse width.
BIT6
DESCRIPTION
0
1.5ms (default)
1
10ms
CCL/ACL THRESHOLD CONTROL REGISTER (0XED)
Definition: Constant Current Control Loop (CCL) kick-in threshold and Average Current Limit (ACL) kick-in threshold control register
Data Length in Bytes: 1
Data Format: Bit Field
Typical: R/W
Protectable: Yes
Default Value: 00h
Units: N/A
Register Name
Format
Bit Position
Access
Function
Default Value
7
6
R/W
R/W
Reserved
0
0
CCL/ACL Threshold Control Register (0xED)
Bit Field
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
ACL Threshold Setting Bits
CCL Threshold Setting Bits
0
0
0
0
0
0
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FN8887.0
November 7, 2016