ISL78226 Datasheet, PDF (29/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Electrical Specifications Refer to the Block Diagram (page 11) and Typical Application Schematics (page 13). Operating conditions
unless otherwise noted: V_VIN = 48V, V_V6 = 6V, V_V12 = 12V, V_BAT12 = 12V, V_PVCC = 5.2V, V_VCC = 5.2V, V_EN = 5.0V, and T_A = -40°C to +125°C. Typicals are
at T_A = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 8) TYP (Note 8) UNIT
Recommended MODE Pin Setting Resistor
Value from MODE pin to VCC- Switching
Mode = Forced PWM/Fault Response =
Latch-off
R_MODE-0
0
Ω
Recommended MODE Pin Setting Resistor
Value from MODE pin to GND- Switching
Mode = DE/Fault Response = Latch-off
R_MODE-1
68.1
kΩ
Recommended MODE Pin Setting Resistor
Value from MODE pin to GND- Switching
Mode = Forced PWM/Fault Response =
Hiccup
R_MODE-2
33.2
KΩ
Recommended MODE Pin Setting Resistor R_MODE-3 Recommended MODE pin setting resistor value R_MODE- 0
Ω
Value from MODE Pin to GND- Switching
from MODE pin to GND- Switching mode =
1
Mode = DE/Fault Response = Hiccup
DE/Fault Response = Latch-off
BT/BK PIN, PWM_EN PIN, PWM_TRI PIN
Input Leakage Current
I_ILK
Forced input voltage at pins (BT/BK, PWM_EN,
-1
PWM_TRI) = 0V to 5V
1
µA
Low Level Input Voltage
V_IL
High Level Input Voltage
V_IH
FAULT/ALERT OUTPUT (XSTAT_FLAG, XHICLAT-F, XSYS_FAIL)
0.8
V
2.0
V
Leakage Current
Pull-down Current
I_{LK_FAULTS} Forced output voltage at pin XSTAT_FLAG = 5V
1
µA
I_{PD_FAULTS} Forced output voltage at pins (XHICLAT-F,
XSYS_FAIL) = 5V
0.5
1.1
2.0
µA
Low Level Output Voltage
V_{OL_FAULTS} Output sink current at pins (XSTAT_FLAG,
XHICLAT-F, XSYS_FAIL) = 3mA
0.1
0.5
V
Low Level Input Voltage
High Level Input Voltage
I²C/PMBUS INTERFACE
V_{IL_FAULTS}
V_{IH_FAULTS}
Input mode at XHICLAT-F
Input mode at XHICLAT-F
0.8
V
2.0
V
Logic Low Level Input Voltage
Logic High Level Input Voltage
Hysteresis
SDA Low Level Output Voltage
Input Current
SCK Clock Frequency
Input Capacitance
SCK Falling Edge to SDA Valid Time
OVER-TEMPERATURE PROTECTION
V_IL
V_IH
V_HYS
V_OL
I_I
f_SCK
C_IN
t_H
SDA (Input mode), SCK Pin
SDA (Input mode), SCK Pin
SDA (Input mode), SCK Pin
I_{OUT_SDA} = 3mA, SDA Pin (Output mode)
SDA (Input mode), SCK Pin
SDA (Input mode), SCK Pin
0
0.8
V
2.1
V_CC
V
0.5
V
0.5
V
-1
1
µA
400
kHz
5
pF
1
µs
Over-Temperature Threshold
160
°C
Over-Temperature Recovery Threshold
145
°C
NOTE:
8. Compliance to datasheet limits are assured by one or more methods; production test, characterization, and/or design.
9. The IC is tested in conditions with minimum power dissipation in the IC, meaning T_A = T_J.
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FN8887.0
November 7, 2016