ISL78226 Datasheet, PDF (18/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Electrical Specifications Refer to the Block Diagram (page 11) and Typical Application Schematics (page 13). Operating conditions
unless otherwise noted: V_VIN = 48V, V_V6 = 6V, V_V12 = 12V, V_BAT12 = 12V, V_PVCC = 5.2V, V_VCC = 5.2V, V_EN = 5.0V, and T_A = -40°C to +125°C. Typicals are
at T_A = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 8) TYP (Note 8) UNIT
V_CC Power-On Reset Threshold (Falling)
V_CC POR Hysteresis
EN
V_{POR_VCC-F}
V_{POR_VCC-HYS}
4.05 4.15 4.25
V
0.4
V
Enable Threshold
V_{TH_EN-R}
V_{TH_EN-F}
V_{TH_EN-HYS}
CLOCK GENERATOR (FSYNC, PLL_COMP, CLKOUT PIN)
Rising
Falling
Hysteresis
1.1
1.2
1.4
V
0.85 0.95 1.10
V
250
mV
FSYNC Voltage
V_FSYNC
R_FSYNC = 46.4kΩ (0.1%) from FSYNC to AGND
500
mV
PWM Switching Frequency
f_CLK
R_FSYNC = 46.4kΩ (0.1%) from FSYNC to AGND
93
100 107
kHz
Minimum Adjustable Switching Frequency f_CLK-Range T_A = +25°C, V_IN = 12V
40
kHz
Maximum Adjustable Switching
Frequency
f_CLK-Range T_A = +25°C, V_IN = 12V
750
kHz
Minimum Synchronization Frequency with
External Clock at FSYNC
f_SYNC-IN T_A = +25°C, V_IN = 12V
40
kHz
Maximum Synchronization Frequency with
External Clock at FSYNC
f_SYNC-IN
T_A = +25°C, V_IN = 12V
750
kHz
Phase Lock Loop Locking Time
t_{PLL_DLY}
From POR to initiation of soft-start.
R_PLLCMP = 3.24k, C_PLLCMP1 = 6.8nF,
C_PLLCMP2 = 6.8nF, R_FSYNC = 40.2k, f_SW =
300kHz
800
µs
High Level CLKOUT Output Voltage
CLKOUT_H
I_CLKOUT = -500µA
V_CC - V_CC -
V
0.5
0.1
Low Level CLKOUT Output Voltage
Output Pulse Width
Phase Shift from PWM-1 Rising Edge to
CLKOUT Pulse Rising Edge
CLKOUT_L I_CLKOUT = 500µA
PWM-1 = OPEN
0.1
0.5
V
1/(12*
f_CLK)
0
°
SYNCHRONIZATION (FSYNC PIN)
Input High Level Threshold
Input Low Level Threshold
Input Minimum Pulse Width - Low Level
Input Minimum Pulse Width - High Level
Delay from Input Pulse Rising to PWM-1
Output Rising Edge
V_{IH_FSYNC}
V_{IL_FSYNC}
tw_{L_FSYNC}
tw_{H_FSYNC}
td_CK-PWM0
PWM-1 = OPEN, Master mode
3.5
V
1.5
V
20
ns
20
ns
25
ns
Input Impedance
REFERENCE VOLTAGE
Z_{IN_FSYNC}
2
kΩ
Reference Accuracy
V_{REF_FB} Measured at FB_BK pin in Buck mode or FB_BT 1.576 1.6 1.620
V
pin in Boost mode
FB Pin Input Bias Current
FLYBACK CONTROLLER
I_{IN_FB}
V_FB = 1.6V, V_TRACK = OPEN
-0.05
0.05
µA
Flyback Error Amplifier Transconductance Gm_{EA_FLY}
Gain
2
ms
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FN8887.0
November 7, 2016