ISL78226 Datasheet, PDF (6/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Pin Description (Continued)
PIN NAME
XHIC-LAT_F
XSYS_FAIL
BT/BK
PWM_EN
CLK_OUT
V12
PGND
GDRV_FLY
SS_FLY
SLOPE_FLY
COMP_FLY
ISP_FLY
ISN_FLY
PLL_COMP
AGND
I/O PIN #
DESCRIPTION
I/O 10 XHIC-LAT_F is an open-drain output used to indicate Hiccup or Latch-off fault and also to communicate hiccup or latch-off
fault status between the multiple ISL78226 devices when used in parallel. This node is required to be pulled up to VCC
with an external resistor. If one of the devices detects Hiccup or Latch-off fault, the pin of the fault detected device will
be driven low and it will pull down the pins of all the other devices connected in parallel. All devices connected in parallel
devices stop all PWM outputs and DRVEN pins will be driven low. When Hiccup mode is selected, the device tries to
restart from soft-start at 500ms intervals until the fault condition is removed. When Latch-off mode is selected, the
device requires the toggling of the EN or PWM_EN pins for restart.
O 11 An open-drain output to indicate a potential serious system failure condition. Pull up this pin with a resistor to VCC or the
MCU I/F supply voltage.
Detects cases where the high-side transistor is shorted, low-side transistor is shorted, the BAT48 is shorted to GND, or
an abnormally large current is sensed at the current sense resistor. When this abnormal condition (continuous
Overcurrent-2 (OC2) or Negative Overcurrent (NOC) in both on and off cycles) continues for three switching cycles, the
device detects this serious failure condition and pulls the XSYS_FAIL pin low. It is recommended that the system have
an emergency protection circuit to disconnect the battery from the system using a fuse or an external path switch when
this signal is pulled low.
NOTE: This flag indicates a potential serious system failure such as H/S or L/S transistor short. This flag does not detect
all of the serious failure conditions, such as when the H/S or L/S transistor is shorted with some resistance. The
combination of fault detection information and an additional external failure detection system is recommended to build
robust failure detection.
I 12 The converter direction selector pin. When this pin is high, the device operates in Boost mode. When this pin is low, the
device operates in Buck mode.
I 13 Bidirectional PWM controller enable/disable control signal. While this pin is Low, the bidirectional PWM controller will
be turned off. When this pin become High, the bidirectional PWM controller will start up from the initialized condition. If
latch-off occurs, toggling this pin will restart the bidirectional PWM output.
NOTE: This pin does not affect the Flyback converter.
O 14 This pin provides a clock signal to synchronize with another ISL78226. The rising edge signal on the CLKOUT pin is the same
timing of rising edge of PWM1 output.
I 15 V12 is used to monitor the bridge driver power supply voltage which is generated by the Flyback regulator. The Flyback
regulator output voltage for the bridge driver is set to 12V internally. Also, this pin is used as the power supply for the
gate drive of Flyback MOSFET.
GND 16 Power and digital ground pin. This pin is a reference of internal digital blocks and is connected to the PWMx output buffer
and Flyback gate driver that generates noisy peak current. Any sensitive analog signal trace should not share common
traces with this driving return path. Connect this pin directly to the ground copper plane and put several vias as close as
possible to this pin. The PGND and AGND should be connected at common solid ground plane.
O 17 PWM output to drive the gate of primary side switching NMOS of Flyback regulator. At the startup of the system, this
driver will be powered by internal backup LDO output (5V typical) and will be switched over to V12 when V12 voltage
exceeds internal backup LDO output voltage.
I 18 Use this pin to set the soft-start time of Flyback regulator output. A capacitor placed from SS_FLY to GND will set up the soft-
start ramp rate and in turn determine the soft-start time. For details, refer to the “Flyback Controller” section on page 44.
I 19 This pin programs the slope compensation for the Flyback controller. A resistor should be connected from the SLOPE_FLY pin
to GND. If this pin is connected to VCC, the Flyback controller will be disabled. For details, refer to the “Flyback Controller”
section on page 44.
I/O 20 The output of the transconductance amplifier of the Flyback controller. Place the compensation network between the
COMP_FLY pin and GND for compensation loop design of Flyback regulator. For details, refer to the “Flyback Controller” section
on page 44.
I 21 Connect this pin to the positive node of the current sense resistor, which is connected to the source of the primary side
switching NMOS of the Flyback regulator. For details, refer to the “Flyback Controller” section on page 44.
I 22 Connect this pin to the GND side of the current sense resistor, which is connected to the source of the primary side
switching NMOS of the Flyback regulator. For details, refer to the “Flyback Controller” section on page 44.
I/O 23 PLL_COMP is used as the compensation node for the PLL. A second order passive-loop filter connected between the
PLL_COMP pin and GND compensates the PLL feedback loop.
GND 24 Analog ground pin; the reference of internal analog circuits. Connect this pin to a large, quiet copper ground plane. In
PCB layout planning, avoid having switching current flowing into the AGND area. The PGND and AGND should be
connected at common solid ground plane.
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FN8887.0
November 7, 2016