ISL78226 Datasheet, PDF (46/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Response Control Register, 0x03[5,4]: V6 Overvoltage Limit Fault
Response Control Register).
If the V12 voltage becomes lower than 75% of the target voltage
(9V), or V6 becomes lower than 5V, the device sets the
corresponding fault status register (0x81[3]: V12 Undervoltage
Limit Status Register, 0x81[1]: V6 Undervoltage Limit Status
Register), pulls down the XSTAT_FLAG, and moves into the Hiccup
or Latch-off mode that is defined by the MODE pin. The fault
response defined by the MODE pin can be overridden by setting
the corresponding control register bits (0x00[7]: Individual Fault
Response Setting bit, 0x03[3,2]: V12 Overvoltage Limit Fault
Response Control Register, 0x03[7,6]: V6 Overvoltage Limit Fault
Response Control Register).
If the device moves into Hiccup mode by V12 or V6 overvoltage
limit, the device stops switching the main controller, Flyback
controller, internal LDOs, and MCU_LDO. After the 500ms
interval, the device restarts automatically from the device
initialization. If the device moves into Latch-off mode by V12 or
V6 overvoltage limit, the device stops the main controller,
Flyback controller, internal LDOs, and MCU_LDO, and waits for
the toggling of EN pin. When the EN pin is toggled, the device will
restart from the device Initialization.
FLYBACK OVERCURRENT PROTECTION
The ISL78226 also monitors the switching current of the Flyback
converter at the primary side.
If the voltage across the Flyback switching current sensing
resistor, which is connected between source side of Flyback
switching MOSFET and GND, exceeds 0.1V, the device sets the
corresponding fault status register (0x81[4]: Flyback Overcurrent
Status Register), pulls down the XSTAT_FLAG, and moves into the
Hiccup or Latch-off mode that is defined by the MODE pin. The
fault response defined by MODE pin can be overridden by setting
the corresponding control register bits (0x00[7]: Individual Fault
Response Setting bit, 0x04[1,0]: Flyback Overcurrent Fault
Response Control Register).
If the device moves into Hiccup mode by Flyback Overcurrent
Protection, the device stops switching of the main controller,
Flyback controller, internal LDOs, and MCU_LDO. After the
500ms interval, the device restarts automatically from the
device initialization. If the device moves into Latch-off mode by
Flyback Overcurrent Protection, the device stops the main
controller, Flyback controller, internal LDOs, and MCU_LDO, and
waits for the toggling of EN pin. When the EN pin is toggled, the
device will restart from the device initialization.
OVERCURRENT PROTECTION
The ISL78226 has multiple levels of overcurrent protection. Each
phase is protected from an overcurrent condition by limiting its
peak current, and the combined total current is protected on an
average basis. Also, each phase has cycle-by-cycle negative
current protection.
CYCLE-BY-CYCLE OVERCURRENT LIMITING (OC1)
The current flowing through the Inductor is monitored by a
Current Sense Resistor (R_SENx) and is protected from the
overcurrent condition (OC1) by limiting its peak current,
cycle-by-cycle basis. When the sensed inductor current reaches
the OC1 threshold (I_SENx = 91µA = 35µA of Sensed Current +
56µA offset), the main switching transistor (high-side transistor
for Buck mode, and low-side transistor for Boost mode) will be
turned off to limit the peak current. When OC1 condition is
detected, the device sets the corresponding status register bit
(0x83[0]: OC1 Status Register, 0x90[5,0]: Fault Phase Indicator
Register) to indicate the fault condition and pull down the
XSTAT_FLAG (an Alert flag). The XSTAT_FLAG alerts the
microcontroller to the fault condition. The external
microcontroller can read out the status register bits (0x83[0]:
OC1 Status Register, 0x90[5,0]: Fault Phase Indicator Register)
via I²C/PMBus to recognize the fault condition.
INDUCTOR PEAK CURRENT OVERCURRENT
PROTECTION (OC2)
If the output current increases even though OC1 is triggered, the
device has 2nd level of overcurrent threshold (OC2) to protect
against further current increase. When the sensed inductor
current reaches to the OC2 threshold (I_SENx = 96µA = 40µA of
Sensed Current + 56µA offset), the device set the corresponding
fault status register (0x83[1]: OC2 Fault Status Register,
0x90[5,0]: Fault Phase Indicator Register), pull down the
XSTAT_FLAG, and move into the Hiccup or Latch-off mode that is
defined by the MODE pin. The fault response defined by MODE
pin can be overridden by setting the corresponding control
register bits (0x00[7]: Individual Fault Response Setting bit, 0x07:
Bat12 Over/Undervoltage Limit Fault Response Control Register,
0x06[7,6]: OC2 Fault Response Control Register, 0x06[5]: Fault
Phase Removal Control Register).
If the device moves into Hiccup mode by the OC2 fault, the device
stops main controller switching but keeps Flyback controller,
Internal LDOs and MCU_LDO active. And after the 500ms
interval, the device restarts automatically from Soft-Start. If the
device moves into Latch-off mode by the OC2 fault, the device
stops main controller but keeps Flyback controller, Internal LDOs
and MCU_LDO active, and wait the toggling of EN_PWM or EN
pin. If the EN_PWM is toggled, the main controller will restart
from the Soft-Start. If the EN pin is toggled, the device stops
Flyback controller, Internal LDOs, MCU_LDO once, and restarts
from the device Initialization.
AVERAGE OVERCURRENT PROTECTION (ACP)
The device continuously monitors the total average output
current at IMON pin. If the IMON pin voltage reaches 2.0V, the
Average Overcurrent Protection (ACP) will be triggered. At ACP,
the device sets the corresponding fault status register (0x83[5]:
ACP Fault Status Register), pulls down the XSTAT_FLAG, and
moves into the Hiccup or Latch-off mode that is defined by the
MODE pin. The fault response defined by the MODE pin can be
overridden by setting the corresponding control register bits
(0x00[7]: Individual Fault Response Setting bit, 0x07: Bat12
Over/Undervoltage Limit Fault Response Control Register,
0x04[5,4]: ACP Fault Response Control Register).
If the device moves into Hiccup mode by the ACP fault, the device
stops the main controller switching but keeps Flyback controller,
internal LDOs, and MCU_LDO active. After the 500ms interval,
the device restarts automatically from soft-start. If the device
moves into Latch-off mode by the ACP fault, the device stops the
main controller but keeps Flyback controller, internal LDOs, and
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November 7, 2016