ISL78226 Datasheet, PDF (24/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Electrical Specifications Refer to the Block Diagram (page 11) and Typical Application Schematics (page 13). Operating conditions
unless otherwise noted: V_VIN = 48V, V_V6 = 6V, V_V12 = 12V, V_BAT12 = 12V, V_PVCC = 5.2V, V_VCC = 5.2V, V_EN = 5.0V, and T_A = -40°C to +125°C. Typicals are
at T_A = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 8) TYP (Note 8) UNIT
Recommended Resistor Value for Slave-2 R_{ADDR_SLV2}
Mode at ADDR Pin to GND
33.2
kΩ
Recommended Resistor Value for Slave-3 R_{ADDR_SLV3}
Mode at ADDR Pin to GND
68.1
kΩ
DRV_EN
Low Level DRV_EN Output Voltage (Master V_{OL_DRVEN} I_{O_DRVEN} = 1mA, ADDR = 0V
Device Only)
0.1
0.5
V
High Level DRV_EN Output Voltage
(Master Device Only)
V_{OH_DRVEN} I_{O_DRVEN} = -1mA, ADDR = 0V
V_CC- V_CC-
V
0.5
0.1
Low Level DRV_EN Input Voltage (Slave
Device Only)
V_{IL_DRVEN} ADDR = VCC
0
0.8
V
High Level DRV_EN Input Voltage (Slave
Device Only)
V_{IH_DRVEN} ADDR = VCC
V_CC-
0.8
V_CC
V
PWMx CONTROL/PWMx OUTPUT
Low Level PWMx Output Voltage
High Level PWMx Output Voltage
V_{OL_PWMx}
V_{OH_PWMx}
I_{O_PWMx} = 1mA
I_{O_PWMx} = -1mA
0.2
0.5
V
V_CC- Vcc-0.2
V
0.5
Tri-State Level PWMx Output Voltage
V_{OTRI_PWMx} I_{O_PWMx} = ±100µA
2.3
2.5
2.7
V
PWMx Pull-Down Current (Effective in
I_{O_PWMx} During Phase count detection period while in
50
µA
Initialization Period Only)
initialization, V_PWMx = 1.0V
Minimum Low Level PWMx Output Pulse
Width
(Boost Mode Default Minimum ON Time)
t_WL-MIN PWMx = open
340
ns
Minimum High Level PWMx Output Pulse
Width
(Buck Mode Default Minimum ON Time)
t_WH-MIN PWMx = open
340
ns
Maximum Low Level PWMx Output Pulse
Width
(Boost Mode Default Maximum ON Duty)
t_ON-MAX-BT PWMx = open
91.7
%
Maximum High Level PWMx Output Pulse
Width
(Buck Mode Default Maximum ON Duty)
t_ON-MAX-BK PWMx = open
91.7
%
PWM_TRI Low Level Input Voltage
PWM_TRI High Level Input Voltage
PHASE DROPPING/ADDING
V_{IL_PWMTRI}
V_{IH_PWMTRI}
0
0.8
V
2.1
V_CC
V
PD_CTRL Pin Pull-up Current (Master
Device Only)
I_{O_PDCTRL} V_PDCTRL = 2V, ADDR = 0V (Master mode only)
36
40
44
µA
PD_CTRL Pin Voltage to Disable Phase
Drop (Master Device Only)
V_{TH_PD-DISA} ADDR = 0V (Master mode)
V_CC- VCC
V
0.5
IMON pin Voltage for Phase Dropping from V_{TH_PD6-64} V_PDCTRL = 2.35V, ADDR = 0V (Master mode)
2.08 2.10 2.12
V
6-Phase to 4-Phase in 6-Phase
Configuration (Master Device Only)
IMON pin Voltage for Phase Dropping from V_{TH_PD6-43} V_PDCTRL = 2.35V, ADDR = 0V (Master mode)
1.98 2.00 2.03
V
4-Phase to 3-Phase in 6-Phase
Configuration (Master Device Only)
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FN8887.0
November 7, 2016