ISL78226 Datasheet, PDF (10/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Pin Description (Continued)
PIN NAME
COMP_BK
ISET
ISHARE
IMON
PD_CTRL
SS
TRACK
VCC
VIN
EPAD
I/O PIN #
DESCRIPTION
I/O 56 The output of the transconductance amplifier for Buck mode operation. Place the compensation network between the
COMP_BK pin and GND for compensation loop design. When BT/BK pin is low, this pin is activated. For setting of
compensation network, refer to the “Adjustable Slope Compensation” on page 38.
I/O 57 ISET is an average output current monitor pin of the phases controlled by this device. The output current from this pin is
proportional to the sum of averaged sense current of each phases at ISENx plus an offset current. A resistor (R_ISET) is
required at this pin to make a reference voltage for current balancing between the devices.
I/O 58 ISHARE pin is used to indicate the average current sensed at all of the current sense resistors in the system when two
or more controller devices are connected in parallel. With a filter comprised of a resistor and a capacitor connected in
parallel from the ISHARE pin to GND, the voltage at the ISHARE pin describes the average output current and is used for
current balancing between the controller devices as described below.
The ISHARE voltage will be compared with the ISET voltage in each device and will generate an error signal that adjusts
the current balance between the devices. For this purpose, the resistor value on this pin should be n*R_ISET, where n
represents the number of devices connected in parallel.
If the controller is used as stand-alone in the system, then connect ISHARE to ISET.
I/O 59 IMON is used for the Average Current Limiting and Average Current Protection. In Boost mode operation, a current that
is proportional to the average inductor current plus an offset current while the L/S transistor is in off state will come out
from this pin. In Buck mode operation, the average inductor current, which is equivalent to the average output current,
will come out from this pin. An external RC filter circuit is required to filter out the pulse current.
The IMON pin will be used for the Average Current Limiting and Protection, and Phase Dropping, too.
- Constant Current Limiting: An average constant output current limiting loop is implemented by comparing the average
current sense signal and a 2.4V reference to have the output average current limited at a constant level.
- Average Current Protection: If IMON pin voltage is higher than 2.7V, the device will move into the Hiccup mode or
Latch-off mode depending on the HIC/LATCH pin configuration.
When a phase dropping operation is selected (PD_CTRL is connected to GND with an external resistor), the voltage at
this pin will be used to determine phase drop timing. For example, if a 6-phase operation is selected, a 6- to 4-phase drop
occurs when IMON voltage is 66% of PD_CTRL. A 4- to 3-phase drop and 3- to 2-phase drop occurs at 50% and 33%,
respectively.
I 60 PD_CTRL pin selects whether phase drop function is enabled or not. If the Phase Drop function is enabled, this pin
provides the reference level of phase dropping/adding threshold.
If the PD_CRTL is connected to VCC, the Phase Drop function is disabled. The device operates in the maximum phase
count defined by the connection of PWM3, 4, 5, and 6 at the initialization stage.
To enable the Phase Drop feature, connect a resistor from PD_CTRL to GND. A 40uA constant current is flowing from this
pin and generates the reference voltage for the phase dropping/adding threshold. The phase dropping/adding threshold
is determined by comparing the PD_CTRL pin voltage and IMON pin. Phase drop thresholds can be overwritten by internal
register settings.
I 61 Use this pin to set the soft-start time. This pin is commonly used for both Buck mode and Boost mode. A capacitor placed from
SS to GND will set up the soft-start ramp rate and, in turn, determine the soft-start time. For Master/Slave operation, the
soft-start current will be increased by the number of controllers used in parallel.
As an example, 5µA will be multiplied by the number of controllers used. If maintaining a soft-start time previously achieved
by a single controller is desired, then a capacitor that is N times larger should be used.
I 62 TRACK is a tracking reference input for both Buck mode and Boost mode operation to provide an external reference for
the device feedback loop to follow.
In default, the device is defined as Digital Tracking. When the analog input is selected by register setting via I²C/PMBus,
the feedback reference tracks the analog voltage applied to this pin. Digital tracking is accomplished by injecting a pulse
width modulated rectangular waveform into the TRACK pin with respect to GND. The output voltage is a function of the
duty ratio of this PWM signal. Connect this pin to VCC if the tracking function is not used.
The lowest voltage of SS, TRACK, or internal reference (1.6V) will be used as the reference of the Buck or Boost mode
voltage error amplifier.
PS (I) 63 This pin provides bias power for the IC analog circuit. An RC filter (10Ω resistor and 1µF capacitor) must be connected
between this pin and PVCC. A minimum 1µF ceramic capacitor should be used between VCC and GND for noise decoupling
purposes.
PS 64 Power Supply input for device wakeup. At the beginning of the startup of the system, the internal backup LDO, reference,
and enable control circuit will be powered from this pin. The Flyback controller will be powered by the backup LDO while
starting up. After the flyback starts up, V6 will be active and the bias current will be supplied by V6.
- EPAD Bottom thermal pad. It is not connected to any electrical potential of the IC. In layout, it must be connected to a PCB large
ground copper plane that does not contain noisy power flows. Put multiple vias (as many as possible) in this pad, connecting
to the ground copper plane to help reduce the IC’s _JA.
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November 7, 2016