ISL78226 Datasheet, PDF (48/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
TABLE 3. ADDRESS CONFIGURATION, MASTER/SLAVE
ADDR PIN
VOLTAGE
RECOMMENDED
CONNECTION OR RESISTOR
AT ADDR PIN
DEVICE ORDER
(MASTER/SLAVE)
GND
GND
Master
1.0V
33.2kΩ
Slave-2
2.05V
68.1kΩ
Slave-3
VCC
VCC
Slave-1
If selected as a slave device, the Flyback controller, MCU_LDO,
BAT12/BAT48 over- and undervoltage detection/protection, and
feedback loop (GM amp, compensation loop, soft-start, and
tracking) of the main controller will be disabled. Also, to
communicate phase dropping information and synchronize with
the master device, the DRV_EN, PD_1, and PD2 pins are set to
input.
The slave device also needs to recognize how many slaves are
connected in parallel to perform the proper phase shifting. For
this purpose, the FB_BT and FB_BK pins are used for the slave
device count indicator. If the system is configured as 1-master/1-
slave operation, connect FB_BT and FB_BK pins of slave device
to GND. If the system is configured as 1-master/2-slave
operation, connect FB_BT and FB_BK pins of slave devices to
VCC. If the system is configured as 1-master/3-slave operation,
connect FB_BT and FB_BK pins of slave devices to GND and VCC,
respectively.
When the system is configured by one master device only,
connect the ADDR pin to GND.
Operating Phase Count Setting and Phase
Shifting
The ISL78226 can work in 2, 3, 4, or 6-phase configuration.
Connecting the PWM5 (or PWM6) to VCC selects 4-phase
operation and each PWM output pulses are shifted in 1/4 cycle
(90°) increments. Connecting the PWM4 to VCC selects 3-phase
operation and each of the PWM output pulses are shifted in 1/3
cycle (120°) increments. Connecting the PWM3 to VCC selects 2-
phase operation and each of the PWM output pulses are shifted in
1/2 cycle (180°) increments.
For the unused ISENxA and ISENxB, a 1kΩ resistor is
recommended to connect ISENxA to ISENxB, and ISENxB to VIN.
I²C/PMBus Communication
The ISL78226 is implemented with an I²C/PMBus compatible
digital interface for the user to monitor and change a few
operating parameters allowing smart control of the regulator.
The Power Management Bus (PMBus) is an open-standard digital
power management protocol. It uses SMBus as its physical
communication layer and includes support for the SMBus Alert
(SALERT). In much the same way as SMBus defines the general
means to manage portable power, PMBus defines the means to
manage power subsystems.
PMBus and SMBus are I²C derived bus standards that are
generally electrically compatible with I²C. They are more robust
(Timeouts Force Bus Reset) and offer more features than I²C,
such as an SMBALERT(SALERT) line for interrupts, Packet Error
Checking (PEC), and Host Notify Protocol.
MONITOR FAULTS AND CONFIGURE FAULT
RESPONSES
When any of the fault conditions are detected, the corresponding
bit of the FAULT_STATUS register will be set to 1 and the XALERT
pin will be pulled low. The I²C/PMBus host controller will get
interrupted by monitoring the XALERT pin and will respond as
follows:
• ISL78226 device pulls XALERT low.
• The host detects that XALERT is low, then performs
transmission with Alert Response Address to find which device
is pulling XALERT low.
• The host talks to the device that is pulling XALERT low. The
actions that the host performs next are up to the system
designer.
Each individual bit of the FAULT_STATUS register can only be
cleared to 0 by writing to that register via I²C/PMBus, or by
CLEAR_FAULTS command, or POR recycle. When all the bits of
FAULT_STATUS register are reset to 0, the XALERT pin is release
to be pulled HIGH. Monitor or reset/clear each individual bit of
the FAULT_STATUS Register (D0h) for its corresponding fault's
status.
Set Operation/Fault Thresholds via
I²C/PMBus
A system controller can change the ISL78226 operating
parameters through the I²C/PMBus interface. These commands
include, but are not limited to, the following:
• Set input/output overvoltage/undervoltage threshold
• Set the fault responses of each individual fault
• Enable or disable the PWM operation of specific phase
• Set constant current control thresholds
Accessible Timing for I²C/PMBus Registers
Status
All the I²C/PMBus command registers are set to default values
during the t₂
page 42. The
-I₂t_{3C/inPiMtiaBliuzsatwioilnl}
period, as shown in Figure 35
be accessible after this part
on
initialization period.
After part start-up, as long as EN and PVCC/VCC are kept HIGH,
all the PMBus registers values are accessible via the PMBus.
When the part is in Latch-off status or Hiccup mode triggered by
any fault, the internal LDO is still enabled and keeps PVCC/VCC
HIGH. All the PMBus register values are accessible via PMBus.
The FAULT_STATUS register values are accessible for the host to
diagnose the type of fault.
Either EN low or PVCC/VCC falling below POR will disable the
ISL78226. All the registers will be reset and not accessible via
PMBus.
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FN8887.0
November 7, 2016