ISL78226 Datasheet, PDF (36/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Boot Refreshing
At the startup of the system or when restarting the dropped phase,
the boot capacitor charge of the external driver may be
discharged. In Buck mode with DE mode is selected, this condition
may cause high-side MOSFET turn-on issue due to insufficient gate
drive voltage. To charge the Boot Capacitor, the low side MOSFET
needs to turn-on. However, because the high-side MOSFET is not
turned on, the low-side MOSFET cannot turn on and, therefore, the
Boot Capacitor cannot be charged. To prevent this issue, the
ISL78226 has a boot refreshing feature for operating in Buck
mode with DE mode selected.
At the startup of the device, the ISL78226 provides Boot refresh
pulses that force low-side MOSFET turn-on for the limited
duration with limited pulse count. As the default, ISL78226
provides eight low-side MOSFET turn-on pulses with the duration
of 1/12 of a switching cycle. This low-side MOSFET on duration
and pulse count can be changed to 1/6 cycle and/or 16-pulses
by an external microcontroller via I²C/PMBus. While the boot
refreshing pulses are provided, the phase shift between the
phases are kept as normal switching.
If the phase is dropped due to the light load condition, the
ISL78226 provides the boot refreshing pulses periodically for the
dropped phases. If the first phase drop is detected, the device
starts the internal counter. When the counter reaches the defined
time duration, the device provides the boot refreshing pulses to
the dropped phases with keeping the proper phase shifting
timing. The default pulse count and low-side MOSFET on duration
will be 4 pulses and 1/24 cycle. As same as the case for device
startup, the pulse count and duration can be selected as 8 pulses
and/or 1/12 cycle.
At a very light-load condition, the device may move into pulse
skipping operation. In this case, as with phase dropping, the
ISL78226 provides the boot refreshing pulses to all the phases.
The interval of boot refreshing, pulse count, and pulse width are
the same as that of phase dropping.
(To prevent turning on active phases randomly in case phase
drop mode is not selected, switch only the Phase-1 (PWM1) while
in pulse skipping operation.)
Current Sharing between Phases
The peak current mode control inherently has current sharing
capability. As shown in Figure 32 on page 37, the current sense
ramp, V_RAMPx, of each phase is compared to the same error
amplifier’s output at the COMP pin by the PWM comparators to
turn off the high-side MOSFET when V_RAMPx reaches COMP
voltage. Thus, the V_RAMPx peaks are controlled to be the same
for each phase. V_RAMPx is the sum of instantaneous inductor
current sense ramp and the compensating slope. Since the
compensating slopes are the same for both phases, the inductor
peak current of each phase is controlled to be the same.
The same mechanism applies to the case when multiple
ISL78226s are configured in parallel for multiphase bidirectional
converter. Basically, the COMP pin of master ISL78226 is tied to
each phase’s current sense ramp peak to be compared with the
same COMP voltage, meaning the inductor peak current of all
the phases are controlled to be the same.
The peak current control scheme works well for sharing current
in most cases. However, if the inductance variation is large, the
power converting of each phase may not be well-controlled. To
provide better current balancing, the ISL78226 has the option to
control the average current of each phase. The device averages
the current of each phase and adds the error information
between the overall averaged current and average current of
each phase to the ramp signal.
Tracking
The ISL78226 has the TRACK input feature, which enables the
user to provide the reference voltage to change the output
voltage.
The default input for the TRACK is digital signal (Digital Tracking)
which enables to control the output voltage based on its duty of
input digital pulse. This can be overridden with analog signal
input (Analog Tracking) by changing the ATRAK/DTRAK control
register bit (0xb0: [4]) to 1.
Figure 4 on page 12 shows the track function block diagram.
VREF_TRK is fed into Gm1 as one of the reference voltages. The
Gm1 takes the lowest voltage of SS, VREF_TRK, and VREF as the
actual reference. When VREF_TRK is the lowest voltage, it is used
as the actual reference voltage for Gm1 and the output voltage
can be adjusted with TRACK signal changes. Under the default
configuration, the VREF_TRK voltage can take 0.8V or higher
voltage. The lower voltage limit is constrained by the minimum
input or output undervoltage limit which is set inside the device
at 50% of the input or output target voltage. If the input or output
undervoltage limit function is ignored by overriding the
corresponding individual fault control registers, the user can set
the VREF_TRK to lower than 0.8V. However, in this case, the Input
or output undervoltage limit fault response will be just flagging
only and no hiccup or latch-off function will be performed, even if
the output or input voltage becomes lower than 50% of their
target.
Since the Gm1 takes the lowest voltage of SS, VREF, and
VREF_TRK, the maximum effective range for VREF_TRK is
determined by the SS or VREF voltage, whichever is lower. For
example, after soft-start, when the SS = 3.4V (typical) and
VREF = 1.6V (default), the maximum effective voltage for
VREF_TRK is 1.6V.
In default, the TRACK pin is configured as digital input (digital
tracking). The average duty of a digital PWM signal applied to the
TRACK pin will be converted to the VREF_TRK. Equation 4
describes the relation between VREF_TRK voltage and duty of
the input digital PWM pulse. A 2-stage RC filter is prepared inside
the device to filter the digital pulses to the analog VREF_TRK
voltage.
V_REFTRK = 2.5  D
(EQ. 4)
The PWM signals’ amplitude at the TRACK pin does not affect
the VREF_TRK accuracy. Only the duty cycle value changes the
VREF_TRK value. The built-in low pass filter converts the PWM
signal’s duty cycle value to a low noise reference. The low pass
filter has a cutoff frequency of 1.75kHz and a gain of -40dB at
400kHz. The 2.5V PWM signal at phase node of Q1 and Q2 will
have around 25mV at VREF_TRK, which is 1.56% of 1.6V
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FN8887.0
November 7, 2016