ISL78226 Datasheet, PDF (35/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
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0
0
50 100 150 200 250 300 350 400 450 500 550 600 650 700 750
f_SW (kHz)
FIGURE 31. RFS vs SWITCHING FREQUENCY
The maximum frequency at each PWM output is 1MHz. If the FS
pin is accidentally shorted to GND or connected to a low
impedance node, the internal circuits will detect this fault
condition and fold back the switching frequency to the 25 kHz
minimal value.
The ISL78226 contains a PHASE LOCK LOOP (PLL) circuit and
has frequency synchronization capability by simply connecting
the SYNC pin to an external square pulse waveform (typically
20% to 80% duty cycle). In normal operation, the external SYNC
frequency needs to be at least 20% faster than the internal
oscillator frequency setting. The ISL78226 will synchronize its
switching frequency to the fundamental frequency of the input
waveform. The frequency synchronization feature will
synchronize the rising edge of the PWM1 clock signal with the
rising edge of the external clock signal at the SYNC pin.
The PLL is compensated with a series resistor-capacitor (R_c and
C_c) from the PLL_COMP pin to GND and a capacitor (C_p) from
PLL_COMP to GND. Typical values are R_c = 6.8kΩ, C_c = 6.8nF,
C_p = 1nF. The typical lock time is around 0.5ms.
The CLK_OUT pin provides a square pulse waveform at the
switching frequency. The amplitude is 5V with approximately
40% positive duty cycle, and the rising edge is synchronized with
the leading edge of PWM1.
Output Voltage Regulation Loop
The resistor divider R_FB2BK and R_FB1BK from BAT12 to FB_BK,
and the resistor divider R_FB2BT and R_FB1BT from BAT48 to FB_BT
can be selected to set the desired output voltage for Buck
converting and Boost converting, respectively. The BAT12 output
voltage V_BAT12 in Buck mode and BAT48 output voltage V_BAT48
in Boost mode can be calculated by Equation 3 and Equation 4,
respectively.
V _{B A T 12}
=
V_R
E
F




1
+
R^{-R----FF----BB----21---BB----KK--}_{}
(EQ. 2)
V _{B A T 48}
=
V_R
E
F




1
+
R^{-R----FF----BB----21---BB----TT-} _{}
(EQ. 3)
Where the V_REF can be either the voltage of soft-start ramp V_SS,
converted digital tracking reference or analog tracking reference
voltage V_{REF_TRK}, and internal system reference voltage
V_{REF_BG}. The error amplifier (Gm) uses the lowest value among
V_SS, V_{REF_TRK} and V_{REF_BG}. The V_SS, V_{REF_TRK} and V_{REF_BG} are
valid for Gm during and after soft-start. In general operation,
V_{REF_TRK} and V_{REF_BG} are normally HIGH before soft-start and
V_SS normally ramps up from a voltage lower than V_{REF_TRK} and
V_{REF_BG}, so V_SS controls the output voltage ramp-up during
soft-start. After soft-start is complete, the output voltage will be
controlled by V_{REF_BG} or V_{REF_TRK} to set to the desired voltage.
Peak Current Mode Control
Figure 30 on page 34 shows the timing diagram of each phase
operation for a 6-phase operation. Each phase’s PWM operation
is initiated by the fixed clock for each phase from the oscillator.
The initiation clock for each phase is separated by 60°. In Buck
mode, ISL78226 provides a high-side MOSFET turn on timing
signal to the driver based on the initiation clock timing. At the
beginning of the PWM cycle, the driver turns on the high-side
MOSFET and, after a preset dead time delay, the inductor current
ramps up. The ISL78226’s Current Sense Amplifiers (CSA)
senses each phase inductor current and generates the current
sense signal I_SENx. The I_SENx is added with the compensating
slope and generates V_RAMPx. When V_RAMPx reaches the error
amplifier (Gm) output voltage, the PWM comparator generates
the high-side MOSFET turn off timing and low side turning on
signal for the driver. Following the high-side turn off/low-side turn
on timing signal, the driver turns off the high-side MOSFET
immediately and turns on the low-side synchronous MOSFET
after the preset dead time. The high-side MOSFET stays off until
the next clock signal comes for the next PWM cycle. The turn-off
timing of the low-side MOSFET is determined by either the PWM
turn-on time at the next PWM cycle or when the inductor current
becomes zero if the Diode Emulation mode is selected.
3-State PWM Control Output
Diode Emulation (DE) mode can be used to turn off control the
synchronous Buck or Boost MOSFETs to turn off when the
inductor current goes to zero. Efficiency is enhanced by not
allowing negative current to flow “backwards” in the inductor
during the off time. The ISL78226 can employ a 3-state PWM
control output. The high level PWM output commands the
high-side power MOSFET to turn on, the low level PWM output
commands the low-side power MOSFET to turn on, and the
middle level (2.5V typical) commands both high-side and low
side power MOSFETs to be turned off. The ISL78420 with a
3-state PWM input, is a recommended driver to realize this
efficient converter system.
Forced PWM is realized if 2-state PWM output is commanded,
i.e., high and low level outputs only. Forced PWM is desired for
the cases of continuous switching, or asynchronous operation.
The user can select the 2-state PWM output by setting the
PWM_TRI pin low. In this case, the PWM outputs indicate the
on/off timing of the main switching MOSFETs.
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FN8887.0
November 7, 2016