ISL78226 Datasheet, PDF (47/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
MCU_LDO active, and waits for the toggling of EN_PWM or EN
pin. If the EN_PWM is toggled, the main controller will restart
from the soft-start. If the EN pin is toggled, the device stops the
Flyback controller, internal LDOs, and MCU_LDO once, and
restarts from the device Initialization.
NEGATIVE OVERCURRENT PROTECTION (NOC)
The ISL78226 also monitors the negative inductor current. If the
negative side of inductor current reaches the Negative
Overcurrent Protection (NOC) threshold, the device turns off the
synchronous switching transistor (low-side transistor in Buck
mode, and high-side transistor in Boost mode) in each cycle to
limit the negative current. When cycle-by-cycle NOC is triggered,
the device sets the corresponding fault status register (0x83[2]:
NOC Fault Status Register, 0x90[5,0]: Fault Phase Indicator
Register) and pulls down the XSTAT_FLAG.
FAULT PHASE REMOVAL (PHASE-DISABLE)
When the Fault Phase Removal option (0x06[5] = 1) is selected,
the ISL78226 can operate without the phases defined by the
Individual Phase Disable Register bits (0x23[5:0]).
The Fault Phase Removal feature enables the device to operate
without the specific phases that might be damaged in cases
where OC2, NOC, and/or external FET short are detected. When
these faults are detected, the ISL78226 moves into
Hiccup/Latch-off mode which is defined by the pin or register
configuration and reports the status. The external MCU
determines the necessity of removing specific phases based on
status information and sets the corresponding register bit of
0x23[5:0]. The ISL78226 will startup by disabling the specified
phases. In this case, phase shifting will not be provided. If more
than half of maximum operation phase count phases are
removed, the device moves into the Latch-off mode and waits for
the toggling of the PWM_EN or EN pin.
OVERRIDING INDIVIDUAL FAULT RESPONSES
The default fault responses (hiccup or latch-off) for all fault
condition are set by the MODE pin configuration. In addition to
the default hardware setting of fault responses, the ISL78226
enables the user to override the individual fault responses by
setting corresponding registers via I²C/PMBus interface. When
the individual fault response setting is selected by setting an
Individual Fault Response Enable/Disable Control” bit (0xB0; [7])
to “1”, all fault responses will follow the settings for Individual
Fault Response Control Registers”. For details on the control
register assignment, refer to “Control and Status Registers” on
page 49.
Operation Mode Setting
The ISL78226 provides several operation modes via the
combination of the BT/BK pin, MODE pin, PWM_TRI pin, and
ADDR pin.
CONVERTER DIRECTION SELECTION
BT/BK pin switches the direction of the converter between Boost
mode and Buck mode. When the BT/BK is logic high (VCC> BT/BK
> VCC-0.7V), the ISL78226 operates in Boost mode. When the
BT/BK is logic low (0V < BT/BK < 0.7V), the device operates in
Buck mode. The BT/BK pin can be controlled by the external
microcontroller to change the converter direction. When the BT/BK
direction is changed on the fly, the device detects the zero cross of
the inductor current, stops the PWMx outputs, and sets DRV_EN
low. The device then moves into the soft-start states to restart in
the opposite direction from the normal soft-start.
PWM OUTPUT MODE SELECTION
PWM_TRI pin selects the 3-state or 2-state output of PWMx
output pins. If PWM_TRI is connected to VCC, PWMx outputs are
set as 3-state output. In this case, the external drivers need to
recognize middle level (2.5V) to turn off both high-side and
low-side MOSFETs. PWMx output high means the high-side
MOSFETs are on and PWMx output low means the low-side
MOSFETs are on. If the PWM_TRI is connected to GND, the PWMx
outputs take 2-state output (i.e., high and low). In this case, the
PWMx outputs indicates the on/off timing of main switching
transistor.
SWITCHING MODE AND FAULT RESPONSE SELECTION
The MODE pin is used to select switching mode (DE mode or
Forced PWM mode) and Fault Response (Hiccup or Latch-off).
This pin has four internal threshold levels to determine the
combination of switching mode and fault response. At the
startup/initialization period of the device, a 30μA current is
sourced from the MODE pin. By connecting this pin to GND, VCC,
or an external resistor, the desired voltage level for the mode
setting will be generated and latched into the device. The relation
between the MODE pin connection (resistor value) and operation
mode are shown in Table 2.
TABLE 2. MODE SELECTION CONFIGURATION
MODE PIN
VOLTAGE
RECOMMENDED
CONNECTION OR
RESISTOR AT MODE PIN
DE MODE OR HICCUP OR
FORCED PWM LATCH
GND
GND
DE
Hiccup
1.0V
33.2kΩ
Forced PWM Hiccup
2.05V
68.1kΩ
DE
Latch-off
VCC
VCC
Forced PWM Latch-off
The DE mode is valid only when the PWM_TRI is connected to
VCC, meaning the 3-state driver is used. If PWM_TRI is connected
to GND, the PWMx output indicates the main switching transistor
is on/off only.
MASTER CONTROLLER AND SLAVE CONTROLLER
SETTING
The connection of ADDR pin determines the main controller
(master) and sub-controller (slave) when the multiple ISL78226 is
used in parallel.
As with the MODE pin, at the startup/initialization of the device, a
30µA current is sourced from the ADDR pin. By connecting this
pin to GND, VCC, or an external resistor from this pin to GND, the
desired voltage level for the device address setting will be
generated and latched into the device. The relation between the
ADDR pin connection (resistor value) and master or slave
selection are shown in Table 3. Up to four devices (and up to 12
phases) can operate in parallel.
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FN8887.0
November 7, 2016