ISL78226 Datasheet, PDF (25/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Electrical Specifications Refer to the Block Diagram (page 11) and Typical Application Schematics (page 13). Operating conditions
unless otherwise noted: V_VIN = 48V, V_V6 = 6V, V_V12 = 12V, V_BAT12 = 12V, V_PVCC = 5.2V, V_VCC = 5.2V, V_EN = 5.0V, and T_A = -40°C to +125°C. Typicals are
at T_A = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 8) TYP (Note 8) UNIT
IMON pin Voltage for Phase Dropping from
3-Phase to 2-Phase in 6-Phase
Configuration (Master Device Only)
V_{TH_PD6-32} V_PDCTRL = 2.35V,
ADDR = 0V (Master mode)
1.89 1.91 1.94
V
IMON pin Voltage for Phase Dropping from V_{TH_PD4-43} V_PDCTRL = 2.35V, ADDR = 0V (Master mode)
2.08 2.10 2.13
V
4-Phase to 3-Phase in 4-Phase
Configuration (Master Device Only)
IMON pin Voltage for Phase Dropping from
3-Phase to 2-Phase in 4-Phase
Configuration (Master device only)
V_{TH_PD4-32} V_PDCTRL = 2.35V,
ADDR = 0V (Master mode)
1.98 2.01 2.03
V
IMON pin Voltage for Phase Dropping from V_{TH_PD3-32} V_PDCTRL = 2.35V, ADDR = 0V (Master mode)
2.06 2.08 2.11
V
3-Phase to 2-Phase in 3-Phase
Configuration (Master device only)
Phase Dropping Masking Time
t_{MASK_PD} After IMON Voltage reached to Phase-Drop
Threshold
15
Cycle
Phase Adding Threshold Hysteresis from
V_{TH_PAD} R_PDCTRL = 60kΩ from PD_CTRL pin to AGND,
60
mV
the Phase Dropping Threshold (Master
ADDR = 0V (Master mode), 6-phase, 4-phase and
device only)
3-phase configuration
Phase Adding Delay Time
t_{d_PA}
After IMON Voltage reached to phase-add
threshold
1
Switching
Cycle
Instant All Phase Adding Threshold
I_{SEN_PAA} Sensed peak current at any individual phases,
80
%
against the OC1 Current Level
V_ISxB = V_BAT12, R_SETxA = R_SETxB = 1kΩ (0.1%),
Instance All Phase Adding Delay Time
t_{d_PAA}
After PWMx sensed current reached at all phase
1
Switching
adding threshold
Cycle
High Level PD_0 Output Voltage (Master
V_{OH_PD_0} I_{OH_PD_0} = -100µA, ADDR = 0V (Master mode)
4.5
5.1
V
Device Only)
Middle Level PD_0 Output Voltage (Master
Device Only)
V_{OM_PD_0}
I_{OM_PD_0} = +/-100µA, ADDR = 0V (Master
mode)
2.25 2.5 2.75
V
Low Level PD_0 Output Voltage (Master
Device Only)
V_{OL_PD_0} I_{OL_PD_0} = 100µA, ADDR = 0V (Master mode)
0.1
0.5
V
High Level PD_1 Output Voltage (Master
V_{OH_PD_1} I_{OH_PD_1} = -100µA, ADDR = 0V (Master mode)
4.5
5.1
V
Device Only)
Low Level PD_1 Output Voltage (Master
Device Only)
V_{OL_PD_1} I_{OL_PD_1} = 100µA, ADDR = 0V (Master mode)
0.1
0.5
V
High Level PD_0 Input Voltage (Slave
Device Only)
V_{IH_PD_0} ADDR = VCC (Slave mode)
4.0
V_CC
V
Middle Level PD_0 Input Voltage (Slave
Device Only)
V_{IM_PD_0} ADDR = VCC (Slave mode)
2.15
2.85
V
Low Level PD_0 Input Voltage (Slave
Device Only)
V_{IL_PD_0} ADDR = VCC (Slave mode)
0
1
V
High Level PD_1 Input Voltage (Slave
Device Only)
V_{IH_PD_1} ADDR = VCC (Slave mode)
4.0
V_CC
V
Low Level PD_1 Input Voltage (Slave
Device Only)
V_{IL_PD_1} ADDR = VCC (Slave mode)
0
1
V
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November 7, 2016