ISL78226 Datasheet, PDF (43/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
VIN = Diode ORed of
BAT48 and BAT12
VIN
EN
1.2V
5V
5.2V
PVCC/VCC
1.6V
Main_REF (Internal)
PWM_CLK (CLKOUT)
fPWM_CLK = 1/12*fPLL_CLOCK
V6
5V ^6V
12V
V12
BT/BK
PWM_EN
DRV_EN
FB_BK
SS
½ VCC
PWM_1,2
VBAT12
Phase_1,2
Boot Cap_1,2
½ VCC
PWM_3~6
Initial Boot Refresh
Pulses
VBAT48
Initial Boot
Refresh Pulses
1.6V
3.4V
VBAT12
Phase_3~6
BAT12
Boot Cap_3~6
t0 t1 t2 t3 t4
t5
t6
t7
t8
t9
t10
t11 t12 t13
t14
FIGURE 36. STARTUP SEQUENCE FOR MAIN PWM CONTROLLER – BUCK MODE/FORCED PWM MODE WITH PHASE-DROP
t₉ - t₁₀: During the period of t₉ to t₁₀, the ISL78226 changes its
switching from non-synchronous mode to synchronous mode
gradually. To avoid the large negative current which will be
caused by the sudden full-on of synchronous FET, the ISL78226
controls the synchronous FETs on-time to gradually increase. This
period is called the soft-on period and has the duration of 15ms
(typical).
t₁₀ - t₁₁: After the completion of the soft-on period at t₁₀, the
converter starts to drop phases during the period of t₁₁ and t₁₂.
In this duration, the high-side MOSFET of the phases to be
dropped will be gradually reduced cycle-by-cycle and will be
finally turned off at t₁₂.
t₁₁ - t₁₂: If the phase dropping function is selected, and the load
current is low enough to reduce the switching phase count, the
controller starts to drop the phases to be dropped during the
period of t₁₁ and t₁₂. In this duration, the On-duty of high-side
MOSFET of the phases to be dropped will be gradually reduced
cycle by cycle and will be finally turned off at t₁₂.
t₁₂ and after: After t₁₂, as long as the load current is not
changing, the controller keeps the same phase count at the
timing of t₁₂. And to keep the bootstrap capacitor for high-side
MOSFETs drive charged, the controller provides boot refresh
pulses every 500u. While in Boot Refreshing period, PWMx of the
dropped phases are pulled low for four clock cycles with
minimum on-time to turn on the low-side MOSFET.
The circuit may not start if VIN is directly set to 64V before EN is
toggled high. It will start if VIN is initially set to a lower voltage
such as 62V, then EN is toggled high. After startup VIN can be
increased to 64V.
LDOs
ISL78226 has three LDOs. The first one, backup LDO, is
implemented for the initial startup of the system. The second
one, the 5.2V internal LDO, is prepared for the main regulated
power rail for the device. The third one, MCULDO is an output
voltage programmable LDO for general purpose use in the
system.
Backup LDO
In a 12V/48V battery system, the converter system needs to startup
with the power rail at either 12V or 48V. To generate the appropriate
voltage for internal analog and logic circuits, typically around 5V, a
backup LDO which generates 5.0V output to PVCC from either 12V
or 48V input is implemented on ISL78226. However, if the power is
always supplied from high voltage rail, the power dissipation of LDO
will be too large to support continuous operation current of the
device and the device temperature will become unnecessarily high.
Therefore, a backup LDO will be switched over with internal 5.2V
LDO, which is supplied by the V6 rail and will be generated by the
device-implemented Flyback converter or external power supply
system after V6 voltage becomes higher than 5V (typical).
The input voltage of backup LDO can tolerate up to 64V (65V
absolute maximum) and has a current limit of 180mA (typical).
Although this is not recommended, the backup LDO can be used
continuously with high load current conditions. With this method,
the power losses at the LDO need to be considered. At high V_IN,
the LDO has significant power dissipation that may raise the
junction temperature where the implemented thermal shutdown
occurs. Figure 37 shows the relationship between maximum
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FN8887.0
November 7, 2016