ISL78226 Datasheet, PDF (49/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Control and Status Registers
To access the ISL78226 Control Registers or Status Registers via the I²C/PMBus Interface, an appropriate device address will need to
be provided. The address IDs for Master device, Slave-1 device, Slave-2 device, and Slave-3 device are 0x4C, Ox4D, 0x4E, and 0x4F,
respectively.
Control Registers
Control registers enable the selection of functions such as analog tracking, inverting of PWM output polarity, individual fault responses for
each fault mode, fault and control threshold setting, maximum/minimum on-duty, and boot-refreshing timing control, etc.
CONTROL REGISTER 1 (0XB0)
Definition: Enables/disables the analog tracking, inverting PWM output polarity, clear faults command, and individual fault settings.
Data Length in Bytes: 1
Data Format: Bit Field
Typical: R/W
Protectable: Yes
Default Value: 00h
Units: N/A
REGISTER NAME
CONTROL REGISTER 1 (0XB0)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Individual
Fault
Response
Control Bit
Clear Faults
PWM_INV
ATRAK/DTR
ACK
Reserved
Default Value
0
0
0
0
0
0
0
0
Individual Fault Response Enable/Disable Control Bit (0xB0: Bit 7)
Enable/disable the individual fault response control by control registers.
VALUE
DESCRIPTION
0 (Default)
Disable individual fault response control.
Use default fault responses defined by the MODE pin setting.
1
Enable individual fault response control by dedicated control registers.
For details, refer to descriptions of each control register.
Clear Faults (0xB0: Bit 6)
Clears all fault bits.
VALUE
0 (Default)
1
DESCRIPTION
Keep the faults
Clear all faults.
After the external MCU reads the fault status, set this bit to “1” to clear the faults, then return to “0” to get next fault. If the error
status is remaining in the system, the error bits will be altered at corresponding registers immediately after this bit returns to
“0”.
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FN8887.0
November 7, 2016