ISL78226 Datasheet, PDF (22/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Electrical Specifications Refer to the Block Diagram (page 11) and Typical Application Schematics (page 13). Operating conditions
unless otherwise noted: V_VIN = 48V, V_V6 = 6V, V_V12 = 12V, V_BAT12 = 12V, V_PVCC = 5.2V, V_VCC = 5.2V, V_EN = 5.0V, and T_A = -40°C to +125°C. Typicals are
at T_A = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 8) TYP (Note 8) UNIT
IMON Output Current (Boost Mode)
I_{IMON_BT} 6-phase, R_SETxA = R_SETxB = 1kΩ (0.1%),
247 258 262
µA
V_ISENxA - V_ISENxB = 30mV, V_ISENxB = V_BAT12,
RIMON = 10.56kΩ
6-phase, R_SETxA = R_SETxB = 1kΩ (0.1%),
225 228.5 232
µA
V_ISENxA - V_ISENxB = 20mV, V_ISENxB = V_BAT12,
RIMON = 10.56kΩ, VIN = 48V, BAT48 = 48V,
BAT12 = 12V, T_A = +25°C
6-phase, R_SETxA = R_SETxB = 1kΩ (0.1%),
216 228.5 234
µA
V_ISENxA - V_ISENxB = 20mV, V_ISENxB = V_BAT12,
RIMON = 10.56kΩ, VIN = 48V, BAT48 = 48V,
BAT12 = 12V
6-phase, R_SETxA = R_SETxB = 1kΩ (0.1%),
V_ISENxA - V_ISENxB = 0mV, V_ISENxB = V_BAT12,
RIMON = 10.56kΩ
157 168 172
µA
ZERO CROSSING DETECTION
6-phase, R_SETxA = R_SETxB = 1kΩ (0.1%),
66
78
83
µA
V_ISENxA - V_ISENxB = -30mV, V_ISENxB = V_BAT12
Sense Current Zero Crossing Detection
(ZCD)
Threshold
OVERCURRENT PROTECTION
V_{TH_ZCD}
Voltage differences at current sense resistor
(V_ISENxA - V_ISENxB), V_ISENxB = VBAT12
R_SETxA = R_SETxB = 1kΩ(0.1%)
1
mV
Cycle-by-Cycle Peak Current Limit (OC1)
Threshold for individual Phases (Buck
mode)
V_OC1
Defined by voltage differences at current sense 26
38
48
mV
resistor (V_ISENxA - V_ISENxB), Buck mode,
V_ISENxB = V_BAT12, R_SETxA = R_SETxB = 1kΩ (0.1%)
Cycle-by-Cycle Peak Current Limit (OC1)
Threshold for individual Phases (Boost
mode)
V_OC1
Defined by voltage differences at current sense 27
38
49
mV
resistor (V_ISENxA - V_ISENxB), Buck mode,
V_ISENxB = V_BAT12, R_SETxA = R_SETxB = 1kΩ( 0.1%)
Cycle-by-Cycle Peak Current Limit (OC1)
Delay
td_OC1
PWMx = Open, Buck mode, from V_OC1-BK
detection at PWMx to PWMx falling
50
ns
Cycle-by-Cycle Peak Current Limit (OC1) to _{td_OC1-FAULT} PWMx = Open, Buck or Boost mode,
50
ns
XSTAT_FLAG Fault Flag Delay
from V_OC1-BK or V_OC1-BT detection at PWMx to
XSTAT_VFLAG Falling
Peak Current Hiccup/Latch-off Protection
V_OC2
Defined by voltage differences at current sense 30
45
55
mV
(OC2) Threshold for individual Phases
resistor (V_ISENxA - V_ISENxB), Buck mode,
(Buck mode)
V_ISENxB = VBAT12, R_SETxA = R_SETxB = 1kΩ(0.1%)
Peak Current Hiccup/Latch-off Protection
V_OC2
Defined by voltage differences at current sense 34
45
57
mV
(OC2) Threshold for Individual Phases
resistor (V_ISENxA - V_ISENxB), Buck mode,
(Boost mode)
V_ISENxB = VBAT12, R_SETxA = R_SETxB = 1kΩ(0.1%)
OC2 Hiccup/Latch-off Blanking Time
td_OC2
Consecutive OC2 detection switching cycles
3
Switching
cycles
OC2 Hiccup Retry Delay
td_OC2-Retry ^{In Hiccup Mode, OC2 detection to next soft-start}
500
ms
starting
OC2 Hiccup/Latch-off Fault Detection to _{td_OC2-FAULT} PWMx = Open, Buck, or Boost mode
50
ns
XHICLAT_F and XSTAT_FLAG Fault Flag
from V_OC2-BK or V_OC2-BT detection at PWMx to
Delay
PWMx stopping, XHICLAT_F and XSTAT_FLAG
falling
High Side Transistor Short Detection in
td_OC2_Short ^{Continuous OC2 condition duration after the OC2}
3
Switching
Buck Mode, or Low Side Transistor Short
hiccup/latch-off triggered
cycles
Detection in Boost Mode for XSYS_FAIL
Falling
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FN8887.0
November 7, 2016