ISL78226 Datasheet, PDF (12/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

Block Diagram (Continued)
ISL78226
ISEN 1B
IS1 B
RSET1B
ISEN 1A
IS1 A
RSET1A
BAT12
ISET
From Slave
CISARE
From Slave
C IMO N
ISHARE
RISHARE
IMON
RIMON
SS
CSS
BAT48
BAT12
RFB 2BT
RFB2 BK
RFB 1BK
FB _BK
FB _BT
RFB 1BT
From MCU
TRK
COMP_BK
COMP_BT
B T/B K
BAT 12
Current
Mirror
IMON1 = ½*(IL1*RSEN1/RSET1+56uA)
Isen1 = ¾*(IL1*RSEN1/RSET1+56uA)
B T/B K
Duplicate for
each Phase (x6)
IMON 6AVG
LPF
Current Mirror
S(IMONxAVG )/n
IMON 2AVG
IMON1AVG
S(IMONxAVG )/n
IMON 1
?IMON 1AVG
S(IMONxAVG )/n
IMON 6
IC2IC Current
Ballancing
S(IMONx)
OC1
ACL
DMAX
FAULT
PW M_ CLK
SQ
R1
R2
85uA
95uA
Isense1
25uA
53uA
OC1
OC2
NOC
ZCD
PWM Control Logic
IMON
Thermal TP
Protection
1.6 V
2.0V
ACL
ACP
Phase Drop/
Phase Shift
Control
PWM_3ST /2 ST
20uA
3-State
Buffer
Mstr
EN
EN
Slave
VCC
1.6V
Gm
SS_PreBias
SS_Clamp
BT/BK
SS
Control
SS _OK
SS_DONE
Analog/Digital
Path Ctrl & LPF
ATRK/
DTRK
Gm
VREF
B T/B K
VCC
FBBT
125% of
VREF
108% of
VREF
75% of
VREF
50% of
VREF
B AT48 _OV_Lim it
Programable
B AT48 _OV
Programable
B AT48 _UV
Programable
B AT48_ UV _LIMIT
FB B K
200% of
VREF
BAT12_OV_Limit
Programable
120% of
VREF
BAT12_OV
Programable
BAT12_UV
80% of
VREF Programable
40% of
VREF
B AT12_ UV _Limit
Main Control Logic
ENA
EN_B T_B K
DE CC HIC LAT BT/BK
MSTR SLV1 SLV2 SLV3
nPhase-EN
B K/B T
SW_ MODE
HIC/LATCH
PV CC _OC
PVCC_OV
PVCC _UV
V12_OV
V12 _UV
V6_OV
V6_UV
FLY_OC
B AT48 _OV
B AT48_ UV
B AT12 _OV
B AT12_ UV
VIN_UV
VIN_OV
Status /Fault
Monitoring
& Control Logic
RFSYNC
FSYNC
PLL_COMP
Internal
Oscillator
SLAVEn
Internal BaseMASTR
nPhase-EN
Clock
PW M_ CLK
Clock
PLL
Timing
Control
Fault/
Sw_mode
Select
INIT
Address
Decoder
I2C/
PMBUS
Control
Logic
INIT
MCUVDD_OV
MCUVDD _UV
M CUVDD _OC
TP
ACP
ACL
NOC
Control NCL
Register/ ^OC1
OC2
Status ZCD
Register
x6
PWM1
DRV_EN
PD_CTRL
PD_1
PD_0
MCU_VDD
XSYS_FAIL
MCU_VDD
XSTAT _FLAG
(SALERT)
MCU_VDD
XHIC-LAT_F
CLKOUT
MODE
BT/BK PWM_EN
ADDR _{SDA SCL}
AGND
PGND TPAD
FIGURE 4. BLOCK DIAGRAM -- BOTTOM
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November 7, 2016