ISL78226 Datasheet, PDF (40/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
2. The voltage at the IMON pin (V_IMON) and the PD_CRTL pin
(VPDCTRL) voltage.
3. Individual phase peak current.
Factors 1 and 2 are similar to the phase dropping scheme. If the
V_ISET is higher than the phase dropping threshold plus the
hysteresis voltage, the dropped phase will be added back one by
one instantly.
The above mentioned phase-adding method can take care of the
condition where the load current increases slowly. However, if the
load is increasing quickly, the IC will use a different phase adding
scheme. The ISL78226 monitors the individual channel current
for all active phases. If any of the phase’s sensed currents hit
85% of OC1 level, all the phases will be added back instantly.
After a fixed 1.5ms delay, the phase dropping circuit will be
reactivated and the system will react by dropping the phase
number to the correct value.
During phase adding, when either phase hits 85% of OC1, there
will be 200µs blanking time such that per-channel Overcurrent
Protection (OC2) will not be triggered during this blanking time.
Phase Dropping/Adding at Slave Device
If multiple ISL78226 parts are connected in parallel, the phase
dropping/adding decision will be made by the master device and
the slave devices will synchronize to that action of the master
device.
To control the phase dropping of slave devices, PD_0 and PD_1
pins will be used. On the master device, PD_0 and PD_1 pins are
configured as output and will be connected to the slave devices’
pins respectively. On the slave device, PD_0 and PD_1 are
configured as input and follow the phase dropping/adding
determined by the master device.
Table 1 shows the relation between PD_0, PD_1, and dropping
phases.
TABLE 1. MASTER/SLAVE PHASE DROP COMMUNICATION
PD_0
PD_1
ACTIVE PHASE COUNT
H
H
6 phases
M (1/2 VCC)
H
4 phases (Drop Phase 6 and 5)
L
H
3 phases (Drop Phase 6,5, and 4)
H
L
2 phases (Drop Phase 6,5,4, and 3)
L
L
(Phase drop is disabled)
Average Current Control
AVERAGE CONSTANT CURRENT CONTROL LOOP (CCL)
In normal PWM operation, to control the output voltage constant,
the PWM pulse is terminated when the ramp voltage that is
proportional to the sensed peak current reaches the error
amplifier control voltage. But in some applications, such as
charging a battery, a constant output current control may be
desired instead of output voltage control. To support such
requirements, a dedicated, average constant Current Control
Loop (CCL) is implemented on ISL78226 to control the average
output current in Buck mode and average input current in Boost
mode to be constant.
As described in “Current Monitoring — IMON” on page 38, the
V_IMON represents the average input or output current in boost or
buck operation, respectively. This V_IMON is sent to the error amplifier
Gm2 input to be compared with the internal CC reference V_{REF_CC},
which is 2.4V as default and can be programmed to different values
by setting the CCL Threshold Control Register (0xDE[2:0]) via
I²C/PMBus™. Gm2 output is driving COMP voltage through a diode
D_CC. Thus, the COMP voltage can be controlled by either Gm1
output or Gm2 output through D_CC.
When V_IMON is lower than the V_{REF_CC}, Gm2 output is kept high,
close to VCC level, and D_CC is blocked and not forward-conducting.
In this condition, the COMP voltage is controlled by the voltage loop
error amplifier Gm1’s output to have output voltage regulated.
If V_IMON reaches V_{REF_CC}, Gm2 output falls, D_CC is forward-
conducting, and Gm2 output overrides Gm1 output to drive COMP.
In this way, the CC loop overrides the voltage loop, meaning V_IMON is
controlled to be constant, achieving average constant current
operation.
An RC network should be connected between the IMON pin and
GND, such that the ripple current signal can be filtered out and
converted to a voltage signal to represent the averaged output
current. The time constant of the RC network should be in the
order of 10 to 100 times slower than the voltage loop bandwidth
so that the CCL circuit does not interfere with the control loop
stability.
AVERAGE OVERCURRENT PROTECTION (ACP)
The ISL78226 monitors the IMON pin voltage (which represents
the averaged total output or input current in Buck mode or Boost
mode, respectively) to detect if Average Overcurrent (OC_AVG)
fault occurs. As shown in Figure 3 on page 11, the comparator
CMP_OCAVG compares V_IMON to internal average overcurrent
threshold voltage (2.6V as default) threshold. When V_IMON is higher
than the threshold, OC_AVG fault is triggered. The corresponding
status register bit (0xD5;[5]) is set to 1 and the XALERT pin is
pulled low.
Power Supply to the Device
To start up the device, VIN needs to be sent to the device initially.
VIN will be used as the temporary power supply until the Flyback
controller starts up and V6 and V12 are supplied to the device. If
Flyback is not used, V6 and V12 need to be provided to the
device externally at the same time or after VIN is provided.
PVCC and VCC will be started from VIN initially and will be
supplied by V6 after V6 becomes higher than the PVCC voltage.
Enabling the Device (EN Pin)
To enable the device, the EN pin needs to be driven higher than
1.2V (typical) by the external enable signal or resistor divider
between VIN and GND. The EN pin has an internal 5kΩ (typical)
pull-down resistor. Also, this pin has an internal 5.2V (typical)
clamp circuit with a 5kΩ (typical) resistor in-series to prevent
excess voltage from being applied to the internal circuits. When
applying the EN signal using resistor divider from VIN, internal
pull-down resistance needs to be considered. Also, the resistor
divider ratio needs to be adjusted as its EN pin input voltage may
not exceed 5.2V.
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FN8887.0
November 7, 2016