ISL78226 Datasheet, PDF (17/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Electrical Specifications Refer to the Block Diagram (page 11) and Typical Application Schematics (page 13). Operating conditions
unless otherwise noted: V_VIN = 48V, V_V6 = 6V, V_V12 = 12V, V_BAT12 = 12V, V_PVCC = 5.2V, V_VCC = 5.2V, V_EN = 5.0V, and T_A = -40°C to +125°C. Typicals are
at T_A = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 8) TYP (Note 8) UNIT
Backup LDO Dropout Voltage (PVCC Pin) V_{DO_BKUPLDO} V_VIN = 5.3V (after startup), V6 = floating,
0.25
V
C_PVCC = 4.7µF from PVCC to PGND, I_VCC = 10mA
Backup LDO Load Regulation (PVCC Pin) dV_BKUPLDO/dI V_V6 = floating, EN = 5V, C_PVCC = 4.7µF from PVCC
O_BKUPLDO ^{to AGND, IO}PVCC ^{= 1mA to 100mA}
0.1
0.5
%
Backup LDO Line Regulation (PVCC Pin) dV_BKUPLDO/dV V_VIN = 5.5V to 55V, EN = 5V, V_V6 = floating, C_PVCC
V6
= 4.7µF from PVCC to AGND
0.2
0.3
%
Backup LDO Current Limit (PVCC Pin)
I_{OC_BKUPLDO} V_VIN = 6V, V_V6 = floating, C_PVCC = 4.7µF from
105 180 220
mA
PVCC to AGND, V_PVCC = 4.5V
Backup LDO Output Short Current (PVCC
I_{OS_PVCC} V_VIN = 6V, V_V6 = floating, C_PVCC = 4.7µF from
90
mA
Pin)
PVCC to AGND, V_PVCC = 0V
INTERNAL LINEAR REGULATOR (INTERNAL LDO)
Internal LDO Output Voltage at PVCC Pin
V_PVCC
EN = 5V, C_PVCC = 4.7µF from AVCC to PGND,
4.94 5.2 5.46
V
I_PVCC = 100mA
Internal LDO Dropout Voltage at PVCC Pin V_{DO_PVCC} V_V6 = 5.5V, C_PVCC = 4.7µF from PVCC to AGND,
0.4
V
I_VCC = 100mA
Internal LDO Load Regulation at PVCC Pin dV_PVCC/dI_{O_PV} EN = 5V, C_PVCC = 4.7µF from PVCC to AGND,
CC
IO_PVCC = 1mA to 100mA
0.1
0.5
%
Internal LDO Line Regulation at PVCC Pin dV_PVCC/dV_V6 V_V6 = 5.7V to 12V, EN = 5V, C_PVCC = 4.7µF from
PVCC to AGND
0.4 0.8
%
Internal LDO Current Limit at PVCC Pin
MCU LINEAR REGULATOR (MCU_LDO)
I_{OC_PVCC}
C_PVCC = 4.7µF from PVCC to AGND
V_PVCC = 4.2V
200
mA
MCUVDD_FB Pin Voltage (MCU_LDO
Output Voltage Accuracy)
MCU_LDO Output Dropout Voltage
V_{MCUVDD_FB} EN = 5V, C_{MCU_VDD} = 10µF from MCU_VDD to
1.14 1.20 1.26
V
GND, I_{MCU_VDD} = 200mA
V_{DO_MCULDO} V_V6 = 5.2V, EN = 5V, setup of V_{MCU_VDD} = 5V,
185
mV
C_{MCU_VDD} = 10µF from MCU_VDD to AGND, no
load
MCU_LDO Output Load Regulation
MCU_LDO Output Line Regulation
LDREG_MCUVDD EN = 5V, Setup of V_{MCU_VDD} = 5V,
C_{MCU_VDD} = 10µF from MCU_VDD to AGND,
IO_MCUVDD = 1mA to 200mA
LINE_
REG_MCUVDD
V_V6 = 5.5V to 12V, EN = 5V, setup of
V_{MCU_VDD} = 5V, C_{MCU_VDD} = 10µF from
MCU_VDD to AGND
0.1
0.5
%
0.1
0.5
%
MCU_LDO Output Current Limit
I_{OCL_MCUVDD} EN = 5V, C_{MCU_VDD} = 10µF, V_{MCU_VDD} = target
250
mA
-1.0V
MCU_LDO Power-Good Upper Limit at
MCULDO_FB Pin
MCU_LDO Power-Good Hysteresis at
MCULDO_FB Pin
MCU_LDO Power-Good Lower Limit at
MCULDO_FB Pin
PG_MCUVDD Leakage Current
V_{PGH_MCUVDD} C_{MCU_VDD} = 10µF from MCU_VDD to AGND,
V_PVCC = 0V
V_{PGL_MCUVDD} C_{MCU_VDD} = 10µF from MCU_VDD to AGND,
V_PVCC = 0V
V_{PGL_MCUVDD} C_{MCU_VDD} = 10µF from MCU_VDD to AGND,
V_PVCC = 0V
I_{LK_PGMCUVDD} Forced output voltage at pins (XSTAT_FLAG,
XHICLAT-F, XSYS_FAIL) = 5V
1.26 1.3 1.34
V
40
mV
1.075 1.100 1.125
V
1
µA
PG_MCUVDD Low Level Output Voltage
VCC POWER-ON RESET (VCC_POR)
V_{OL_FAULTS} Output sink current at PG_MCUVDD = 3mA
0.1
0.5
V
VCC Power-On Reset Threshold (Rising)
V_{POR_VCC-R}
4.35 4.5 4.75
V
Submit Document Feedback ₁₇
FN8887.0
November 7, 2016