ISL78226 Datasheet, PDF (89/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Operating Phase Count (0xDD: Bit 3:1)
These bits indicate current operating phase count.
0XDC BIT3
0XDC BIT2
0XDC BIT1
1
1
1
6-phase operation
1
0
1
4-phase operation
0
1
1
3-phase operation
1
1
0
2-phase operation
1
0
0
Not assigned
0
1
0
Not assigned
0
0
1
Not assigned
0
0
0
Not assigned
DESCRIPTION
Configured Maximum Operating Phase Count (0xDD: Bit 6:4)
These bits indicate the maximum operating phase count, which is configured by the hardware connection of PWMx pins and latched at the
initialization period of device startup.
0XDC BIT6
0XDC BIT5
0XDC BIT4
DESCRIPTION
0
0
0
6-phase operation (All PWMx are not connected to VCC for 6-phase configuration)
0
0
1
4-phase operation (PWM5 is connected to VCC for 4-phase configuration)
0
1
0
3-phase operation (PWM4 is connected to VCC for 3-phase configuration)
0
1
1
2-phase operation (PWM 3 is connected to VCC for 2-phase configuration)
1
0
0
Not assigned
1
0
1
Not assigned
1
1
0
Not assigned
1
1
1
Setting Error (PWM1 or PWM2 is connected to VCC at startup of the device)
SYSTEM STATUS REGISTER-3 (0XDF)
Definition: System Status register 3
Data Length in Bytes: 1
Data Format: Bit Field
Typical: R/W
Protectable: Yes
Default Value: 00h
Units: N/A
REGISTER NAME
Format
Bit Position
Access
Function
Default Value
7
6
R
R
FSYNC Status
0
0
SYSTEM STATUS REGISTER-3 (0XDF)
Bit Field
5
4
3
2
1
0
R
R
R
R
R
R
PLL_COMP Clock Source Soft ON SS Complete PLL Locked Clock Source
Short
Changed Completed
-
-
-
-
-
-
Clock Source Indicator (0xDF: Bit 0)
Indicates which external clock or internal clock is used as PWM clock source.
0XDD BIT0
DESCRIPTION
0
Internal Clock (clock frequency is determined the resistor connected between FSYNC and GND).
1
External Clock
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FN8887.0
November 7, 2016