ISL78226 Datasheet, PDF (41/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
To disable or reset all fault status, the EN pin needs to be driven
lower than 1.1V (typical). When the EN pin is driven low, the
ISL78226 turns off all of the blocks to minimize the off-state
quiescent current.
VIN
EN
FROM
EXTERNAL EN
CONTROL
5k
5M
5.2V
CLAMP
VCC
+
-
TO INTERNAL
CIRCUITS
1.2V
FIGURE 34. ENABLE BLOCK
Initialization and Startup Sequence
INITIALIZATION AND INTERNAL BIAS CIRCUIT STARTUP
Startup Timing Diagram 1 in Figure 35 shows the typical
initialization and startup sequences of internal blocks before the
main PWM controller startup with ISL78226. Prior to the
converter start initialization for startup, the BAT48, BAT12, and
V_IN voltages need to be applied to the device (t0 to t1). The EN
pin voltage then needs to be set higher than its rising threshold
(1.2V typical) (t1) to startup internal regulators. Following the EN
pin rise, the internal Backup LDO starts up and the PVCC/VCC
voltages become higher than the rising POR threshold (t₂). At
this point, the controller begins initialization.
Detailed descriptions on startup procedures for the initialization
period and internal power supplies are described in the following
sections:
t₀ - t₁: The enable comparator holds the ISL78229 in shutdown
until the V_EN rises above 1.2V (typical) at the time of t₁.
t₁ - t₂: After EN is set to higher than its rising threshold, V_PVCC/VCC
will gradually increase and reach the internal power-on reset
(POR) rising threshold 4.5V (typical) at t₂.
t₂ - t₃: During t₂ - t₃, the ISL78229 will go through an
initialization process to detect certain pin configurations (ADDR,
MODE, PWMx) to latch in the selected operation modes. The time
duration for t₂ - t₃ is typicalically 195µs.
After the t3, the I²C/PMBus communication can be established
to check the device and system status and to configure the
device operation mode.
t₃ - t₄: During this period, the ISL78226 will wait until the internal
PLL circuits are locked to the preset oscillator frequency. When
PLL locking is achieved at t₄, the oscillator will generate output
at the CLKOUT pin. The time duration for t₃ - t₄ depends on the
PLLCOMP pin configuration. The PLL is compensated with a
series resistor-capacitor (R_PLL and C_PLL1) from the PLLCOMP pin
to GND and a capacitor (C_PLL2) from PLLCOMP to GND. At
100kHz switching frequency, typical values are R_PLL = 3.24kΩ,
C_PLL1 = 6.8nF, C_PLL2 = 1nF. With this PLLCOMP compensation,
the time duration for t₃ - t₄ is around 0.7ms.
t₄ - t₆: The PLL locks the frequency t₄ and the system is ready to
start the Flyback controller, internal LDO, and MCU_LDO. If
Flyback block is used, the Flyback circuit starts its soft-start at t4.
The Flyback circuitry pre-biases the SS_FLY pin voltage to be
equal to V_{FB_FLY} just after the t₄, which will take around 50µs.
The Flyback controller starts switching at this time and the
V6/V12 voltages rise following the SS_FLY pin. After V6 and V12
reach their target voltage ranges and the Flyback soft-start
period is completed, the SS_FLY pin voltage reaches higher than
3.4V (typical) at t5 and internal LDO starts up. Internal LDO will
switch the main power supply path to the PVCC/VCC from the VIN
to V6 to reduce the power loss at the power path transistor of the
LDO output stage. With this power source transition, the PVCC
voltage from Internal LDO will become 5.2V. At timing t5, the
MCU_LDO also starts up. The output voltage of the MCU_LDO can
be defined by the resistor network connected between MCULDO
output, FB_MCULDO, and GND.
If the Flyback block is not used, connect SS_FLY to VCC. In this
case, V6 and V12 must be applied externally. When the
SS_FLY = VCC, V6 > 4.9V, and V12 > 9.1V conditions are met,
following the t₄, the internal LDO and MCU_LDO can start up.
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FN8887.0
November 7, 2016