ISL78226 Datasheet, PDF (72/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
MAXIMUM ON-DUTY SETTING REGISTER (0XBF)
Definition: Maximum on-duty setting register
Data Length in Bytes: 1
Data Format: Bit Field
Typical: R/W
Protectable: Yes
Default Value: 00h
Units: N/A
Register Name
Format
Bit Position
Access
Function
Default Value
7
R/W
0
6
R/W
0
Maximum On-Duty Setting Register (0xBF)
Bit Field
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
Maximum On-Duty Setting Bits
0
0
0
0
0
0
Maximum On-Duty Setting Bits (0xBF: Bit 2:0)
Sets the maximum on-duty of the main switching FET (maximum on-duty of H/S FET for Buck mode and maximum on duty of L/S FET for
Boost mode
BIT2
BIT1
BIT0
DESCRIPTION
0
0
0
91.7% (default)
0
0
1
95.8%
0
1
0
87.5%
0
1
1
83.3%
1
0
0
79.2%
1
0
1
75.0%
1
1
0
Not assigned (75%)
1
1
1
Not assigned (75%)
BOOT REFRESH CONTROL REGISTER (0XEC)
Definition: Boot refresh control register/phase drop enable blanking time control register
Data Length in Bytes: 1
Data Format: Bit Field
Typical: R/W
Protectable: Yes
Default Value: 00h
Units: N/A
Register Name
Format
Bit Position
Access
Function
Default Value
7
R/W
Reserved
0
6
R/W
Phase Drop Enable
Blank Time After
Phase-Added
0
Boot Refresh Control Register (0xEC)
Bit Field
5
4
3
R/W Not Assigned
R/W
Reserved Boot Refresh Boot Refresh
Pulse Count Pulse Width
Before SS Control Bit
0
0
0
2
1
0
R/W
R/W
R/W
Boot Refresh Interval Control Bits
0
0
0
Submit Document Feedback ₇₂
FN8887.0
November 7, 2016