ISL78226 Datasheet, PDF (5/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

Pin Configuration
ISL78226
ISL78226
(64 LD 10x10 TQFP)
TOP VIEW
ADDR
MODE
SLOPE_BT
SLOPE_BK
FB_BT
FB_BK
COMP_BT
COMP_BK
ISET
ISHARE
IMON
PD_CTRL
SS
TRACK
VCC
VIN
48
49
64
1
EPAD
33
32
PWM4
PWM3
PWM2
PWM1
PD_1
PD_0
PWM_TRI
FSYNC
AGND
PLL_COMP
ISN_FLY
ISP_FLY
COMP_FLY
SLOPE_FLY
SS_FLY
17
GDRV_FLY
16
Pin Description
PIN NAME
EN
PVCC
V6
MCUVDD
MCUVDD_FB
PG_MCUVDD
SCK
SDA
XSTAT_FLAG
I/O PIN #
DESCRIPTION
I
1 Device Enable/shut-off control pin. When EN pin is driven above 1.4V, the ISL78226 is active. The operating mode
depends on the configurations of the mode setting pins, control registers, and fault register status. The fault status will
be kept while the EN pin is high unless internal power on reset (POR) becomes low. When the EN pin is driven below 0.7V
the device clears all fault statuses and goes into shut-down mode. While in shut-down mode, the current consumption
of the device will be less than 1µA.
PS 2 Output of the internal linear regulator that provides bias for internal analog and logic circuits. The PVCC operating range
(O)
is 4V to 5.4V. A ceramic capacitor of 4.7µF minimum is recommended between PVCC and PGND for noise decoupling.
This capacitor should be connected as close as possible to PVCC and PGND.
I
3 V6 is biased by an external ~6V source and is also one of the control loop feedback inputs for the Flyback converter.
O 4 The output of MCULDO to supply the MCU or an external general purpose circuit. The output voltage of MCULDO can be
adjusted with an external feedback resistor network which is connected between this output, MCUVDD_FB, and AGND.
I
5 Feedback for the MCUVDD output. The midpoint of a resistor voltage divider between MCUVDD and AGND is connected
to this pin and is compared with the internal reference voltage (1.2V) to regulate the MCUVDD output voltage.
O 6 An open-drain output for MCUVDD voltage power-good indication. Pull this pin up with a resistor to supply voltage of MCU
I/F. When the output voltage is within the regulation limit and soft-start is complete, the internal pull down of this pin is
released and this pin will be pulled high by the external resistor. This pin will be pulled low when the output OV or UV
condition is detected.
I
7 I²C/SMBus communication clock input. Requires external pull up.
I/O 8 I²C/SMBus communication data input/output. Requires external pull up.
O 9 An open-drain output to indicate any status changes at the internal status register. Pull up this pin with a resistor to VCC
or supply voltage of MCU I/F. This is including both fault condition detection and warning condition detection. To
recognize the status, MCU should read the status registers via I²C/PMBUS.
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FN8887.0
November 7, 2016