ISL78226 Datasheet, PDF (59/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
INDIVIDUAL FAULT RESPONSE CONTROL REGISTER 5 (0XB6)
Definition: Cycle-by-Cycle Overcurrent 2 (OC2) fault response setting
Data Length in Bytes: 1
Data Format: Bit Field
Typical: R/W
Protectable: Yes
Default Value: 00h
Units: N/A
REGISTER NAME
Format
Bit Position
Access
Function
Default Value
INDIVIDUAL FAULT RESPONSE CONTROL REGISTER 5 (0XB6)
Bit Field
7
6
5
4
3
2
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OC2 Fault Response
Control Bits
Reserved
0
0
0
0
0
0
0
0
R/W
0
Cycle-by-Cycle OC2 Fault Response Control Bits (0xB6: Bit 7:6)
If the individual fault response enable/disable control bit (0xB0[7]) is “1”, the device selects the fault response when detecting
Overcurrent 2 condition at any of the PWM switching channels. If the individual fault response enable/disable control bit (0xB0[7]) is
“0”, the “MODE” pin setting will be used for the fault control and this register setting will be ignored.
BIT1
BIT0
DESCRIPTION
0
0
Flagging only (Default)
When the overcurrent 2 (OC2) condition is detected at any of the PWM switching channels, the corresponding fault
status register (0xD5[1]) will be set to “1”, and XALERT will be pulled low. Also, the fault-detected channel
information can be obtained by reading a status register 0xDA[5:0]. The system continues to operate. No hiccup or
latch-off responses.
0
1
Hiccup (Auto Restart)
When the overcurrent 2 (OC2) condition is detected at any of the PWM switching channels, the corresponding fault
status register (0xD5[1]) will be set to “1”, and XALERT will be pulled low. Also, the fault-detected channel
information can be obtained by reading a status register 0xDA[5:0]. At the same time, the system stops PWM
switching. The PWM switching will recover automatically 500ms (typical) after the OC2 condition is removed.
1
0
Latch-off
When the overcurrent 2 (OC2) condition is detected at any of the PWM switching channels, the corresponding fault
status register (0xD5[1]) will be set to “1”, and XALERT will be pulled low. Also, the fault detected channel
information can be obtained by reading a status register 0xDA[5:0]. At the same time, the system stops PWM
switching. The PWM switching will not be recovered automatically. To recover the PWM switching, toggle PWM_EN
or EN.
1
1
Flagging only (same as “0,0”)
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FN8887.0
November 7, 2016