ISL78226 Datasheet, PDF (87/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
OC2 at Phase-6 Indicator (0xDA: Bit 5)
The device detected the OC2 condition at Phase-6.
0XDA BIT5
0
OK: No OC2 condition is detected.
1
OC2 is detected at Phase-6.
DESCRIPTION
SYSTEM STATUS REGISTER-1 (0XDC)
Definition: System Status register 1
Data Length in Bytes: 1
Data Format: Bit Field
Typical: R/W
Protectable: Yes
Default Value: 00h
Units: N/A
REGISTER NAME
Format
Bit Position
Access
Function
Default Value
7
R
PWM Output
Ready
-
6
R
Reserved
0
SYSTEM STATUS REGISTER-1 (0XDC)
Bit Field
5
4
3
R
R
R
PWM Output Protection
Mode
Mode
Switching
Mode
-
-
-
2
1
R
R
Device Position
-
-
Converter Direction (0xDC: Bit 0)
Indicates the current converter direction, Buck or Boost. Reflects the BT/BK pin status.
0XDC BIT0
DESCRIPTION
0
Buck mode
1
Boost mode
0
R
Converter
Direction
0
Device Position (0xDC: Bit 2:1)
Indicates the device position in the system: Master, Slave-1, Slave-2, or Slave-3. Reflects the ADDR pin configuration, which is latched at
the initialization period of device startup.
0XDC BIT2
0XDC BIT1
DESCRIPTION
0
0
Master
0
1
Slave-1
1
0
Slave-2
1
1
Slave-3
Switching Mode (0xDC: Bit 3)
Indicates the current switching mode (DE mode or Forced PWM mode) of the device. The register reflects the MODE pin configuration,
which is latched at the initialization period of device startup.
0XDC BIT3
DESCRIPTION
0
DE mode
1
Forced PWM mode
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FN8887.0
November 7, 2016