ISL78226 Datasheet, PDF (90/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
PLL Locked Indicator (0xDF: Bit 1)
Indicates whether PLL is properly locked or not. If PLL is not locked, the system clock is not provided from CLKOUT and the PWM operation
will not start.
0XDF BIT1
DESCRIPTION
0
PLL is not locked.
1
PLL is locked and CLKOUT is ready to use.
Soft-Start Complete Indicator (0xDF: Bit 2)
Indicates whether the Soft-Start period of main converter is finished or not.
0XDF BIT2
DESCRIPTION
0
Soft-start period is not completed.
1
Soft-start period is completed.
Soft-On Period Complete Indicator (0xDF: Bit 3)
Indicates whether the soft-on period (Transition period from non-synchronous to synchronous (Forced PWM or DE) at the end of soft-start)
is completed or not.
0XDF BIT3
DESCRIPTION
0
Soft-on period.
1
Completed soft-on period (Normal operation).
Clock Source Change Indicator (0xDF: Bit 4)
Indicates when the clock source is changed from internal to external or external to internal.
0XDF BIT4
DESCRIPTION
0
Clock source is stable (not changed).
1
Clock source change is detected.
PLL_COMP Short (0xDF: Bit 5)
Indicates PLL_COMP is shorted.
0XDF BIT5
DESCRIPTION
0
PLL_COMP is normal.
1
PLL_COMP is shorted to GND. PLL cannot lock and system may not startup.
FSYNC Current Status (0xDF: Bit 7:6)
FSYNC pin connection status indicator. (Error indicator)
0XDF BIT7
0XDF BIT6
DESCRIPTION
0
0
OK: FSYNC is connected to frequency setting resistor properly or driven by external clock.
0
1
FSYNC may be shorted to GND.
1
0
FSYNC is open or shorted to VCC.
1
1
Not used
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FN8887.0
November 7, 2016