ISL78226 Datasheet, PDF (58/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Average Overcurrent Fault Control Bit (0xB4: Bit 5:4)
When the individual fault response enable/disable control bit (0xB0[7]) is “1”, the device selects the fault response when Average
overcurrent protection (average output overcurrent in Buck mode and average input overcurrent in Boost mode) condition is detected.
When the individual fault response enable/disable control bit (0xB0[7]) is “0”, the “MODE” pin setting will be used for the fault control and
this register setting will be ignored.
BIT5
BIT4
DESCRIPTION
0
0
Flagging only (Default)
When Average Overcurrent Protection (ACP) (average output overcurrent in Buck mode and average input overcurrent
in Boost mode) condition is detected, the corresponding fault status register (0xD5[5]) will be set to “1”, and XALERT
will be pulled low. The system continues to operate. No hiccup or latch-off responses.
0
1
Hiccup (Auto Restart)
When Average Overcurrent Protection (ACP) (average output overcurrent in Buck mode and average input overcurrent
in Boost mode) condition is detected, the corresponding fault status register (0xD5[5]) will be set to “1”, and XALERT
will be pulled low. At the same time, the system stops PWM switching. The PWM switching will recover automatically
500ms (typical) after the ACP condition is removed.
1
0
Latch-off
When Average Overcurrent Protection (ACP) (average output overcurrent in Buck mode and average input overcurrent
in Boost mode) condition is detected, the corresponding fault status register (0xD5[5]) will be set to “1”, and XALERT
will be pulled low. At the same time, the system stops PWM switching. The PWM switching will not recover
automatically when the ACP condition is removed. To recover the switching, toggle PWM_EN or EN.
1
1
Flagging only (same as “0.0”)
Flyback Primary Side Switching FET Short Fault Control Bit (0xB2: Bit 7)
If the individual fault response enable/disable control bit (0xB0[7]) is “1”, the device selects the fault response when detecting the shot
condition at the primary side switching FET of Flyback. If the individual fault response enable/disable control bit (0xB0[7]) is “0”, the
“MODE” pin setting will be used for the fault control and this register setting will be ignored.
BIT7
DESCRIPTION
0
(Default)
When detecting the shot condition at primary side switching FET of Flyback, the corresponding fault status register (0xD8[4]) will be
set to “1”, XALERT will be pulled low, and XSYS_FAIL will be pulled low to stop the system.
Flyback and PWMx switching will be stopped. To recover, toggle EN.
1
Flagging only
When detecting the shot condition at primary side switching FET of Flyback, the corresponding fault status register (0xD8[4]) will be
set to “1” and XALERT will be pulled low. The XSYS_FAIL pin will not be pulled low.
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FN8887.0
November 7, 2016