ISL78226 Datasheet, PDF (44/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
allowed backup LDO output current and input voltage. The curves
are based on +25°C/W thermal resistance _JA of the package.
200
180
160
140
120
100
80
60
40
20
0
5
TA = +25°C
TA = +75°C
TA = +125°C
10 15 20 25 30 35 40 45 50 55 60
VIN (V)
FIGURE 37. POWER DERATING CURVE
Internal 5.2V LDO
After the backup LDO starts up and V6 voltage, which is generated
by Flyback or external power supply system, becomes higher than
5.2V (typical), the internal 5.2V LDO will switch over to the backup
LDO and supply 5.2V (typical) output voltage to PVCC. The internal
5.2V LDO has a fixed 5.2V output and up to 200mA (typical)
current limit capability. A 10µF, 10V, or higher X7R typical
ceramic capacitor is recommended between PVCC to GND. At
low VIN operation, when the internal LDO is saturated or the load
current becomes too large to force output voltage to be lower
than 5V, the backup LDO will turn on again to supply the
additional current. If the system falls into this condition, power
loss will need to be considered as described in “Backup LDO” on
page 43.
The output of this LDO, PVCC, is mainly used for the internal logic
and PWM driver output. With VCC connected to PVCC as in the
typical application, PVCC also supplies other internal analog
circuitry. To provide a quiet power rail to the internal analog
circuitry, it is recommended to place an RC filter between PVCC
and VCC. A minimum of 1µF ceramic capacitor from VCC to
ground should be used for noise decoupling purposes. Since
PVCC is providing noisy logic current, a small resistor like 10Ω or
smaller between the PVCC and VCC helps to prevent the noises
interfering from PVCC to VCC.
MCULDO
The ISL78226 implements a general purpose LDO, called
MCU_LDO, to supply the regulated power rail for external MCU
and/or other logic/analog functions. V6 is used as the power supply
for the MCU_LDO. The output voltage of MCU_LDO can be
configured with a resistor network between MCU_VDD,
MCUVDD_FB, and GND. Since the reference voltage at MCUVDD_FB
is set at 1.2V (typical), the output voltage of MCULDO at MCU_VDD
pin will be defined as Equation 11.
V_MCUVDD
=
1.2



1

+
RR_{-----MM-----CC----UU----VV----DD----DD----FF----BB----12-}
(EQ. 11)
To stabilize the output of the MCU_LDO, it is recommended to
place a 10µF, 10V or higher rated X7R ceramic capacitor
between MCU_VDD and GND. The MCU_LDO has its own power
good threshold to indicate the MCU_LDO output is within the
target range. An open-drain logic output of PG_MCUVDD will be
pulled low if the MCU_VDD output is lower or higher than the
target range. The rising threshold of undervoltage and
overvoltage of MCU_VDD power good is 91.7% and 108.3%,
respectively, and with 2% of hysteresis. The MCU_LDO has the
current limit at 250mA (typical).
Flyback Controller
The ISL78226 implements a controller for a Flyback converter
consisting of an external FET, a current sensing shunt, and a
Flyback transformer. The capability exists to generate a 6V and
12V bus that can be used to power the V6 and V12 pins on the IC.
V6 bias circuits are internal to the ISL78226 and V12 biases to
the external FET drivers.
The design follows typical Flyback converter guidelines. A
Flyback transformer, which is really a three-winding, coupled
inductor, is selected that is able to absorb energy due to current
buildup in its primary winding during the FET on-time. The
Flyback transformer then delivers that energy during the FET
off-time from its two secondary windings. Enough energy must
be absorbed during the FET on-time to support the power
required during a switching cycle. The energy absorbed by the
end of the FET on-time is stated in Equation 12:
E = ¹²--  L_PRI  I_{P2 RI}
(EQ. 12)
The primary current slope during the FET on-time will be
proportional to the primary input voltage and inversely
proportional to the Flyback transformer primary inductance.
Multiplying the current slope by the on-time yields the peak
current as shown in Equation 13.
I_PK = ^T---_L-^o---_P-ⁿ---_R-^---_I^V--_M--^F---_A-^L--_R-^Y----_YI--^N--
(EQ. 13)
The peak primary current will be detected by a shunt resistor
connected between the FET source and ground. The voltage
across this shunt resistor must be detected via a Kelvin
connection and fed back to the ISL78226 through ISP_FLY and
ISN_FLY. Use caution; since one lead of the shunt resistor goes to
ground a layout tool may allow this connection to be non-Kelvin.
If the voltage fed back from this shunt resistor is too high, then
the FET will be turned off prematurely and current limiting will
occur.
The secondary turns ratio should be 2/1 because the output
voltage ratio is V12/V6. The output voltage feedback loop
regulation target is satisfied when V6 ~ 6V and V12 ~ 12V.
Fault Handling
The ISL78226 continuously monitors the input and output
voltage of the 12V and 48V battery rails, inductor current of the
individual phases, the average output current in Buck mode, the
average input current in Boost mode, the Flyback output voltages
(6V/12V), the Flyback primary side switching current, and the
PVCC/VCC voltages to detect any abnormal voltage or current
conditions if present. If a fault condition is detected, depending
upon the level of the fault condition, the ISL78226 provides the
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November 7, 2016