ISL78226 Datasheet, PDF (7/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Pin Description (Continued)
PIN NAME
FSYNC
PWM_TRI
PD_0
PD_1
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
DRV_EN
ISEN1A
ISEN1B
I/O PIN #
DESCRIPTION
I 25 FSYNC pin is used to adjust the internal oscillator frequency or external synchronous clock input.
The oscillator switching frequency is adjusted with a resistor from this pin to GND.
If the external synchronous clock is applied to this pin, the internal oscillator locks to the rising edge. There is a 25ns
(typical) delay from the FSYNC pin’s input clock rising edge to PWM1 rising edge.
I 26 This pin enables the Tri-Level of the PWM output signal. Pulling the PWM_TRI to VCC enables Tri-Level PWM output
signals, then the PWM output can be at the 2.5V tri-level condition. To use the Tri-Level output, the external driver needs
to be applicable to this function. ISL78420 is an example.
Pulling this pin to GND forces the PWM output to be two-level logic.
I/O 27 PD_0 and PD_1 are used to control the phase dropping between the multiple ISL78226 in parallel. If the controller is
configured as Master Controller, the PD_0 and PD_1 are configured as output to indicate the number of the operation
I/O 28 _{phases of the system to slave devices.}
The Slave Controller receives the phase dropping indicator signal from PD_0 and PD_1 pins. The relation between the
phase dropping and PD_0 and PD_1 levels are as below. Refer to Table 1.
Phases are dropped or added three switching cycles after the changes of PD_0 and PD_1 signal for both master and
slave controllers.
The PD_0 and PD_1 signals are also used to indicate the Boot-Refresh timing to the slave devices from the master
device. When the master detects the Boot-Refreshing timing while operating in Buck mode, the PD_0 and/or PD_1 pins
will be toggled to low level for one PLL-Clock period (1/12 of PWM clock cycle), which initializes the boot refresh timing
of the slave devices.
O 29 Pulse Width Modulation (PWM) output for Phase 1. Connect this output to the PWM input of an external driver IC of
Phase 1.
O 30 Pulse Width Modulation (PWM) output for Phase 2. Connect this output to the PWM input of an external driver IC of
Phase 2.
O 31 Pulse Width Modulation (PWM) output for Phase 3. Connect this output to the PWM input of an external driver IC of
Phase 3.
If this pin is connected to VCC, the device operates in 2-phase mode and PWM3 to PWM6 output will be disabled.
O 32 Pulse Width Modulation (PWM) output for Phase 4. Connect this output to the PWM input of an external driver IC of
Phase 4.
If this pin is connected to VCC, the device operates in 3-phase mode and PWM4 to PWM6 output will be disabled.
O 33 Pulse Width Modulation (PWM) output for Phase 5. Connect this output to the PWM input of an external driver IC of
Phase 5.
If this pin is connected to VCC, the device operates in 4-phase mode and PWM5 and PWM6 output will be disabled.
O 34 Pulse Width Modulation (PWM) output for Phase 6. Connect this output to the PWM input of an external driver IC of
Phase 6.
If this pin is connected to VCC, the device operates in 4-phase mode and PWM5 and PWM6 output will be disabled.
O 35 Driver Enable signal output pin. This pin will be connected to the Enable pin of the driver. When the ISL78226 is ready
to output the PWM signal, this DRV_EN signal goes high. If the ISL78226 is disabled, the hiccup/latch-off fault condition
occurs, or the MCU overrides the DRV_EN register to be low (disabled), then this output will be pulled low and disable the
drivers.
I 36 Current Sense Amplifier (CSA) 1 input. With a combination of ISEN1B and gain setting resistor R_SET1A and R_SET1B, the
current flowing at Current Sense Resistor-1 will be converted to the sensed current signal and forwarded into the device.
Connect ISEN1A at the negative side of Current Sense Resistor-1 in Buck mode configuration. Ultimately senses the
BAT12 voltage side of the current sensing shunt through the filter, refer to Figure 4 on page 12. The resistive shunt MUST
be Kelvin connected, do not allow this connection to take place anywhere else on the BAT12 plane. The sensed current
information is used for peak current mode control, average current control, and overcurrent protections.
I
37 The other side of Current Sense Amplifier (CSA) 1 input. With a combination of ISEN1A and gain setting resistors, R_SET1A
and R_SET1B, the current flowing at Current Sense Resistor-1 will be converted to the sensed current signal and forwarded
into the device. Connect ISEN1B at the positive side of Current Sense Resistor-1 in Buck mode configuration. Ultimately
senses the inductor side of the current sensing shunt through the filter, refer to Figure 4. The resistive shunt MUST be
Kelvin connected. The sensed current information is used for peak current mode control, average current control, and
overcurrent protections.
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FN8887.0
November 7, 2016