ISL78226 Datasheet, PDF (23/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Electrical Specifications Refer to the Block Diagram (page 11) and Typical Application Schematics (page 13). Operating conditions
unless otherwise noted: V_VIN = 48V, V_V6 = 6V, V_V12 = 12V, V_BAT12 = 12V, V_PVCC = 5.2V, V_VCC = 5.2V, V_EN = 5.0V, and T_A = -40°C to +125°C. Typicals are
at T_A = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 8) TYP (Note 8) UNIT
Cycle-by-Cycle Negative Peak Current
Limit (NOC) Threshold for Individual
Phases (Buck Mode)
Cycle-by-Cycle Negative Peak Current
Limit (NOC) Threshold for Individual
Phases (Boost mode)
Cycle-by-Cycle Negative Peak Current
Limit (NOC) Delay
V_NOC
Defined by voltage differences at current sense -38
-30
-24
mV
resistor (V_ISENxA - V_ISENxB), Buck mode,
V_ISENxB = V_BAT12, R_SETxA = R_SETxB = 1kΩ (0.1%)
V_NOC
Defined by Voltage differences at current sense -39
-30
-25
mV
resistor (V_ISENxA - V_ISENxB), Buck mode,
V_ISENxB = V_BAT12, R_SETxA = R_SETxB = 1kΩ (0.1%)
td_NOC
PWMx = Open, Buck mode,
50
ns
from V_NOC-BK detection at PWMx to PWMx rising
and XSTAT_FLAG falling
Cycle-by-Cycle Negative Peak Current
td_NOC-FAULT ^{PWMx = Open, Buck mode,}
50
ns
Limit (NOC) Fault Flag Delay
from V_NOC-BK or V_NOC-BT detection at PWMx to
XSTAT_FLAG falling
Low Side Transistor Short Detection in
td_ONC
Continuous negative overcurrent limit exceeding
3
Switching
Buck Mode or High Side Transistor Short
duration
cycles
Detection in Boost Mode for XSYS_FAIL
Falling
AVERAGE OVERCURRENT PROTECTION AND CONSTANT CURRENT LIMITING LOOP
Average Constant Current Limit (ACL)
Reference Voltage
V_{ACL_REF} IMON pin voltage while average constant current 2.33 2.4 2.47
V
limiting is working 0x28[2,0] = 0,0,0
0x28[2,0] = 0,0,1
2.3
0x28[2,0] = 0,1,0
2.2
0x28[2,0] = 0,1,1
2.1
0x28[2,0] = 1,0,0
2.0
0x28[2,0] = 1,0,1
1.9
0x28[2,0] = 1,1,0
1.8
0x28[2,0] = 1,1,1
1.7
Average Overcurrent Protection (ACP)
Hiccup/Latch-off Fault Threshold at IMON
pin (Buck Mode)
V_{TH_ACP}
Selected LATCHOFF/HICCUP response.
0x28[5,3] = 0,0,0
0x28[5,3] = 0,0,1
2.57 2.7 2.83
V
2.6
0x28[5,3] = 0,1,0
2.5
0x28[5,3] = 0,1,1
2.4
0x28[5,3] = 1,0,0
2.3
0x28[5,3] = 1,0,1
2.2
0x28[5,3] = 1,1,0
2.1
0x28[5,3] = 1,1,1
2.0
Hiccup Retry Delay when Average
td_ACP-Retry ^{In Hiccup Mode, ACP detection to next soft-start}
500
ms
Overcurrent Protection Detected
starting
MASTER/SLAVE SETTING
ADDR Output Current (Initialization Period I_{O_ADDR} Initialization period only, ADDR pin voltage = 0V 26
30
34
µA
Only)
Recommended Resistor Value for Master R_{ADDR_MSTR}
Mode at ADDR Pin to GND
0
Ω
Recommended Resistor Value for Slave-1 R_{ADDR_SLV1}
Setting at ADDR Pin to VCC
0
Ω
Submit Document Feedback ₂₃
FN8887.0
November 7, 2016