ISL78226 Datasheet, PDF (55/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
INDIVIDUAL FAULT RESPONSE CONTROL REGISTER 3 (0XB3)
Definition: V12 and V6 (Flyback output or external input when Flyback is not used) overvoltage and undervoltage fault response setting
Data Length in Bytes: 1
Data Format: Bit Field
Typical: R/W
Protectable: Yes
Default Value: 00h
Units: N/A
REGISTER NAME
Format
Bit Position
Access
Function
Default Value
INDIVIDUAL FAULT RESPONSE CONTROL REGISTER 3 (0XB3)
Bit Field
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
V6 Undervoltage Fault
Control Bits
V6 Overvoltage Fault
Control Bits
V12 under Voltage Fault V12 Overvoltage Fault
Control Bits
Control Bits
0
0
0
0
0
0
0
0
V12 Overvoltage Fault Control Bit (0xB3: Bit 1:0)
When the individual fault response enable/disable control bit (0xB0[7]) is “1”, the device selects the fault response when V12 exceeds
the overvoltage threshold. When the individual fault response enable/disable control bit (0xB0[7]) is “0”, the “MODE” pin setting will be
used for the fault control and this register setting will be ignored.
BIT1
BIT0
DESCRIPTION
0
0
Flagging only (Default)
When V6 voltage exceeds the overvoltage threshold, the corresponding fault status register (0xD3[2]) will be set to
“1”, and XALERT will be pulled low. The system continues to operate. No hiccup or latch-off responses.
0
1
Hiccup (Auto Restart)
When V12 voltage exceeds the overvoltage threshold, the corresponding fault status register (0xD3[2]) will be set to
“1”, and XALERT will be pulled low. At the same time, the system stops PWM switching. The PWM switching will
recover automatically 500ms (typical) after the overvoltage condition is removed.
1
0
Latch-off
When V12 voltage exceeds the overvoltage threshold, the corresponding fault status register (0xD3[2]) will be set to
“1”, and XALERT will be pulled low. At the same time, the system stops PWM switching. The PWM switching will not
recover automatically when the overvoltage condition is removed. To recover the switching, toggle PWM_EN or EN.
1
1
Flagging only (same as “0,0”)
V12 Undervoltage Fault Control Bit (0xB3: Bit 3:2)
When the individual fault response enable/disable control bit (0xB0[7]) is “1”, the device selects the fault response when V12 voltage
becomes lower than the undervoltage threshold. When the individual fault response enable/disable control bit (0xB0[7]) is “0”, the
“MODE” pin setting will be used for the fault control and this register setting will be ignored.
BIT1
BIT0
DESCRIPTION
0
0
Flagging only (Default)
When V12 output voltage becomes lower than the undervoltage threshold, the corresponding fault status register
(0xD3[4]) will be set to “1”, and XALERT will be pulled low. The system continues to operate. No hiccup or latch-off
responses.
0
1
Hiccup (Auto Restart)
When V12 voltage becomes lower than the undervoltage threshold, the corresponding fault status register (0xD3[4])
will be set to “1”, and XALERT will be pulled low. At the same time, the system stops PWM switching. The PWM
switching will recover automatically 500ms (typical) after the undervoltage condition is removed.
1
0
Latch-off
When V12 voltage becomes lower than the undervoltage threshold, the corresponding fault status register (0xD3[4])
will be set to “1”, and XALERT will be pulled low. At the same time, the system stops PWM switching. The PWM
switching will not recover automatically when the undervoltage condition is removed. To recover the switching, toggle
PWM_EN or EN.
1
1
Flagging only (same as “0.0”)
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FN8887.0
November 7, 2016