ISL78226 Datasheet, PDF (88/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
Protection Mode (0xDC: Bit 4)
Indicates the current pin configuration of Protection mode. Reflects the MODE pin configuration, which is latched at the initialization
period of device startup. If the individual fault response setting is used, ignore this status bit and used individual fault response setting
register values.
0XDC BIT4
DESCRIPTION
0
Latch-off mode
1
Hiccup mode
PWM Output Mode (0xDC: Bit 5)
Indicates the PWM output mode, 3-state or 2-state. Reflects the PWM_TRI pin configuration, which is latched at the initialization period of
the device startup.
0XDC BIT5
DESCRIPTION
0
2-state output
1
3-state output
PWM Output Ready (0xDC: Bit 7)
Indicates whether the PWM output is ready or not.
0XDC BIT7
DESCRIPTION
0
PWM output is not ready.
(For slave devices, this bit is always “0” because it is not controlling the DRV_EN).
1
PWM output is ready.
SYSTEM STATUS REGISTER-2 (0XDD)
Definition: System Status register 2
Data Length in Bytes: 1
Data Format: Bit Field
Typical: R/W
Protectable: Yes
Default Value: 00h
Units: N/A
REGISTER NAME
Format
Bit Position
Access
Function
7
R
Reserved
SYSTEM STATUS REGISTER-2 (0XDD)
Bit Field
6
5
4
3
2
1
R
R
R
R
R
R
Configured Maximum Phase Count
Operating Phase Count
Default Value
0
-
-
-
-
-
-
Phase Drop Enabled or Disabled Indicator (0xDD: Bit 0)
Indicates whether the Phase Drop/Add function is enabled or disabled. Reflects the PD_CTRL pin configuration.
0XDD BIT0
DESCRIPTION
0
Phase Drop/Add function is Enabled.
1
Phase Drop/Add function is Disabled.
(For Slave devices, this bit is always “1” because phase drop is controlled by the Master device)
0
R
Phase Drop
Enabled/Disa
bled
-
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FN8887.0
November 7, 2016