ISL78226 Datasheet, PDF (42/94 Pages) Intersil Corporation – Cycle-by-cycle peak current limiting

ISL78226
48V
BAT48
BAT12
12V
VIN
VIN=Diode ORed of
BAT48 and BAT12
EN
1.2V
PVCC
VCC
VCC=Filtered
output of PVCC
Main_REF (Internal)
1.6V
5V ^{Backup LDO output will be forwarded to PVCC until V6>PVC5C.2V}
4.6V (PVCC POR)
Backup LDO output will be used for
Power Supply (VCC) of Main BG before
Flyback startup
Switch Over Backup LDO to Internall LDO with
changing Main Power Source from VIN to V6 at
V6>Backup LDO and Flyback Soft-Start is
completed
PLL_COMP
PLL_LOCK (Internal)
PWM_CLK (CLKOUT)
PLL_Sta
rt
Backup LDO output will be used for Power
PLL_Lock
Supply (VCC) of CLKGEN before Flyback startup
fPWM_CLK = 1/12*fPLL_CLOCK
FLYBK_EN (Internal)
SS_FLY
V6
V12
MCU_VDD
Backup LDO output will be used for Power
Supply (VCC) of Flyback before Flyback startup
Flyback PVCC output is pre-biased to
MCU_VDD by Backup_LDO
5V ^6V
12V
MCU_LDO startup when V6>Backup LDO
and Flyback Soft-Start is completed
PGVDDMCU
PWM_EN
DRV_EN
PWMx
t0
½ VCC
t1 t2
t3
t4
t5
FIGURE 35. CIRCUIT INITIALIZATION AND SOFT-START
Startup of Main Controller
After t5, the system is ready to start the main PWM controller. It
is recommended to reconfigure the device operation mode and
individual fault handling between t5 and t6, if necessary.
Figure 36 on page 43 shows the timing diagram of the main
controller startup with Buck mode, Forced PWM mode, and
Phase Drop-Enabled case examples.
t₆ - t₇: While PWM_EN is kept lower than its falling threshold
(1.0V typical), the ISL78226 keeps the main controller turned off
by keeping DRV_EN signal low. Also, the PWMx outputs that
control high-side and low-side MOSFET switching are kept to
1/2VCC for the purpose of turning off both high-side and low side
MOSFETs. When PWM_EN becomes higher than its rising
threshold (1.2V typical), the DRV_EN output will be pulled high to
enable the drivers to control MOSFETs based on PWMx signals.
Just after the DRV_EN output goes high, ISL78226 pulls PWMx
outputs low with minimum, low-side, on-time pulse width for
8-clock cycles to charge the high-side bootstrap capacitor (Boot
Refresh).
t₇ - t₉: After the boot refresh period, the controller moves into the
soft-start period. At the beginning of the soft-start period (t₇), the
device pre-charges the SS pin voltage to the FB_BK voltage in
order to minimize the time lag to start soft-start when the output
voltage is pre-biased. After the completion of SS pre-biasing, the
SS pin ramps up by charging the soft-start capacitor, which is
connected between the SS pin and GND, with the constant
soft-start current (I_ss). The COMP voltage starts to ramp up as
well. Drivers are enabled during this period but not allowed to
switch until COMP becomes greater than the current sense ramp
offset. Once the COMP pin voltage becomes greater than the
current sense ramp offset, the PWMx outputs begin switching
the drivers. The output voltage ramps up while the FB voltage is
following the SS ramp during this soft-start period. At t₈, the
output voltage reaches regulation level and the FB voltage
reaches 1.6V. After the SS voltage reaches 1.6V at t₈, SS
continues ramping up until it reaches the SS clamp voltage
(VSSPCLAMP) 3.47V at t₉, indicating that the SS pin ramp-up is
completed. At t₉, the ISL78226 generates an internal soft-start
complete signal.
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FN8887.0
November 7, 2016