BD82QM67-SLJ4M Datasheet, PDF (931/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Intel® Management Engine Subsystem Registers (D22:F[3:0])
23.4.2.6
KTIIR—KT Interrupt Identification Register
(KT—D22:F3)
Address Offset: 02h
Default Value: 00h
Attribute:
Size:
RO
8 bits
The KT IIR register prioritizes the interrupts from the function into 4 levels and records
them in the IIR_STAT field of the register. When Host accesses the IIR, hardware
freezes all interrupts and provides the priority to the Host. Hardware continues to
monitor the interrupts but does not change its current indication until the Host read is
over. Table in the Host Interrupt Generation section shows the contents.
23.4.2.7
Bit
Description
7
FIFO Enable (FIEN1)— RO. This bit is connected by hardware to bit 0 in the FCR
register.
6
FIFO Enable (FIEN0)— RO. This bit is connected by hardware to bit 0 in the FCR
register.
5:4 Reserved
3:1
IIR STATUS (IIRSTS)— RO. These bits are asserted by the hardware according to
the source of the interrupt and the priority level.
Interrupt Status (INTSTS)— RO.
0
0 = Pending interrupt to Host
1 = No pending interrupt to Host
KTFCR—KT FIFO Control Register (KT—D22:F3)
Address Offset: 02h
Default Value: 00h
Attribute:
Size:
WO
8 bits
When Host writes to this address, it writes to the KTFCR. The FIFO control Register of
the serial interface is used to enable the FIFOs, set the receiver FIFO trigger level and
clear FIFOs under the direction of the Host.
When Host reads from this address, it reads the KTIIR.
Bit
Description
Receiver Trigger Level (RTL)— WO. Trigger level in bytes for the RCV FIFO. Once
the trigger level number of bytes is reached, an interrupt is sent to the Host.
00 = 01
7:6
01 = 04
10 = 08
11 = 14
5:3 Reserved
2
XMT FIFO Clear (XFIC)— WO. When the Host writes one to this bit, the hardware
will clear the XMT FIFO. This bit is self-cleared by hardware.
1
RCV FIFO Clear (RFIC)— WO. When the Host writes one to this bit, the hardware
will clear the RCV FIFO. This bit is self-cleared by hardware.
FIFO Enable (FIE)— WO.When set, this bit indicates that the KT interface is working
0
in FIFO node. When this bit value is changed the RCV and XMT FIFO are cleared by
hardware.
Datasheet
931