BD82QM67-SLJ4M Datasheet, PDF (846/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Serial Peripheral Interface (SPI)
21.4.17 OPMENU—Opcode Menu Configuration Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 98h
Default Value:
0000000000000000h
Attribute:
Size:
R/W
64 bits
Eight entries are available in this register to give GbE a sufficient set of commands for
communicating with the flash device, while also restricting what malicious software can
do. This keeps the hardware flexible enough to operate with a wide variety of SPI
devices.
Note:
It is recommended that GbE avoid programming Write Enable opcodes in this menu.
Malicious software could then perform writes and erases to the SPI flash without using
the atomic cycle mechanism. This could cause functional failures in a shared flash
environment. Write Enable opcodes should only be programmed in the Prefix Opcodes.
Bit
Description
63:56
55:48
47:40
39:32
31:24
23:16
15:8
7:0
Allowable Opcode 7 — R/W. See the description for bits 7:0
Allowable Opcode 6 — R/W. See the description for bits 7:0
Allowable Opcode 5 — R/W. See the description for bits 7:0
Allowable Opcode 4 — R/W. See the description for bits 7:0
Allowable Opcode 3 — R/W. See the description for bits 7:0
Allowable Opcode 2 — R/W. See the description for bits 7:0
Allowable Opcode 1 — R/W. See the description for bits 7:0
Allowable Opcode 0 — R/W. Software programs an SPI opcode into this field for use
when initiating SPI commands through the Control Register.
This register is not writable when the SPI Configuration Lock-Down bit (MBARB +
00h:15) is set.
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846
Datasheet