BD82QM67-SLJ4M Datasheet, PDF (475/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

LPC Interface Bridge Registers (D31:F0)
13.1.38.4
FVEC3—Feature Vector Register 3
FVECIDX.IDX: 0011b
Default Value: See Description
Attribute:
Size:
Power Well:
RO
32 bit
Core
Bit
Description
31:14 Reserved
Data Center Manageability Interface (DCMI) Capability — RO
13 _{0 = Capable}
1 = Disabled
Node Manager Capability — RO
12 _{0 = Capable}
1 = Disabled
11:0 Reserved
13.1.39
RCBA—Root Complex Base Address Register
(LPC I/F—D31:F0)
Offset Address: F0–F3h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bit
Bit
Description
31:14
Base Address (BA) — R/W. Base Address for the root complex register block decode
range. This address is aligned on a 16-KB boundary.
13:1 Reserved
0
Enable (EN) — R/W. When set, this bit enables the range specified in BA to be claimed
as the Root Complex Register Block.
Datasheet
475