BD82QM67-SLJ4M Datasheet, PDF (763/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

PCI Express* Configuration Registers
19.1.9
CLS—Cache Line Size Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 0Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0
Cache Line Size (CLS) — R/W. This is read/write but contains no functionality, per
the PCI Express* Base Specification.
19.1.10
PLT—Primary Latency Timer Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 0Dh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:3 Latency Count. Reserved per the PCI Express* Base Specification.
2:0 Reserved
19.1.11
HEADTYP—Header Type Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 0Eh
Default Value: 81h
Attribute:
Size:
RO
8 bits
Bit
Description
Multi-Function Device — RO.
7
0 = Single-function device.
1 = Multi-function device.
Configuration Layout— RO. This field is determined by bit 2 of the MPC register
(D28:F0-5:Offset D8h, bit 2).
6:0 _{00h = Indicates a Host Bridge.}
01h = Indicates a PCI-to-PCI bridge.
Datasheet
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