BD82QM67-SLJ4M Datasheet, PDF (544/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

LPC Interface Bridge Registers (D31:F0)
13.10.1
GPIO_USE_SEL—GPIO Use Select Register
Offset Address: GPIOBASE + 00h
Default Value: B96BA1FFh
Lockable:
Yes
Attribute:
Size:
Power Well:
R/W
32-bit
Core for 0:7, 16:23,
Resume for 8:15, 24:31
Bit
31:0
Description
GPIO_USE_SEL[31:0] — R/W. Each bit in this register enables the corresponding
GPIO (if it exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
NOTES:
1.
The following bits are always 1 because they are always unmultiplexed: 8, 15,
24, 27, and 28.
2.
After a full reset (RSMRST#) all multiplexed signals in the resume and core
wells are configured as their default function. After only a PLTRST#, the GPIOs
in the core well are configured as their default function.
3.
When configured to GPIO mode, the multiplexing logic will present the inactive
state to native logic that uses the pin as an input.
4.
By default, all GPIOs are reset to the default state by CF9h reset except
GPIO24. Other resume well GPIOs' reset behavior can be programmed using
GP_RST_SEL registers.
5.
Bit 29 can be configured to GPIO when SLP_LAN#/GPIO29 Select Soft-strap is
set to 1 (GPIO usage).
6.
GPIO18, GPIO25, and GPIO26 are mobile only GPIOs.
13.10.2
GP_IO_SEL—GPIO Input/Output Select Register
Offset Address: GPIOBASE +04h
Default Value: F6FF6EFFh
Lockable:
Yes
Attribute:
Size:
Power Well:
R/W
32-bit
Core for 0:7, 16:23,
Resume for 8:15, 24:31
Bit
31:0
Description
GP_IO_SEL[31:0] — R/W.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have
no effect. The value reported in this register is undefined when programmed as
native mode.
0 = Output. The corresponding GPIO signal is an output.
1 = Input. The corresponding GPIO signal is an input.
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