BD82QM67-SLJ4M Datasheet, PDF (816/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Serial Peripheral Interface (SPI)
21.1.5
FDATA0—Flash Data 0 Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 10h
Default Value:
00000000h
Attribute:
Size:
R/W
32 bits
Bit
31:0
Description
Flash Data 0 (FD0) — R/W. This field is shifted out as the SPI Data on the Master-Out
Slave-In Data pin during the data portion of the SPI cycle.
This register also shifts in the data from the Master-In Slave-Out pin into this register
during the data portion of the SPI cycle.
The data is always shifted starting with the least significant byte, msb to lsb, followed
by the next least significant byte, msb to lsb, etc. Specifically, the shift order on SPI in
terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-…8-23-22-…16-31…24
Bit 24 is the last bit shifted out/in. There are no alignment assumptions; byte 0 always
represents the value specified by the cycle address.
Note that the data in this register may be modified by the hardware during any
programmed SPI transaction. Direct Memory Reads do not modify the contents of this
register.
21.1.6
FDATAN—Flash Data [N] Register
(SPI Memory Mapped Configuration Registers)
Memory Address:
Default Value:
SPIBAR + 14h
SPIBAR + 18h
SPIBAR + 1Ch
SPIBAR + 20h
SPIBAR + 24h
SPIBAR + 28h
SPIBAR + 2Ch
SPIBAR + 30h
SPIBAR + 34h
SPIBAR + 38h
SPIBAR + 3Ch
SPIBAR + 40h
SPIBAR + 44h
SPIBAR + 48h
SPIBAR + 4Ch
00000000h
Attribute: R/W
Size:
32 bits
Bit
31:0
Description
Flash Data N (FD[N]) — R/W. Similar definition as Flash Data 0. However, this
register does not begin shifting until FD[N-1] has completely shifted in/out.
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