BD82QM67-SLJ4M Datasheet, PDF (691/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Integrated Intel^® High Definition Audio Controller Registers
17.1.1.12
HDBARL—Intel^® High Definition Audio Lower Base Address
Register (Intel^® High Definition Audio—D27:F0)
Address Offset: 10h–13h
Default Value: 00000004h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:14
Lower Base Address (LBA) — R/W. Base address for the Intel^® High Definition Audio
controller’s memory mapped configuration registers. 16 Kbytes are requested by
hardwiring bits 13:4 to 0s.
13:4 Reserved
3
Prefetchable (PREF) — RO. Hardwired to 0 to indicate that this BAR is NOT
prefetchable
2:1
Address Range (ADDRNG) — RO. Hardwired to 10b, indicating that this BAR can be
located anywhere in 64-bit address space.
0
Space Type (SPTYP) — RO. Hardwired to 0. Indicates this BAR is located in memory
space.
17.1.1.13
HDBARU—Intel^® High Definition Audio Upper Base Address
Register (Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 14h–17h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
31:0
Description
Upper Base Address (UBA) — R/W. Upper 32 bits of the Base address for the Intel^®
High Definition Audio controller’s memory mapped configuration registers.
17.1.1.14 SVID—Subsystem Vendor Identification Register
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset:
2Ch–2Dh
Default Value:
0000h
Function Level Reset: No
Attribute:
Size:
R/WO
16 bits
The SVID register, in combination with the Subsystem ID register (D27:F0:2Eh),
enable the operating environment to distinguish one audio subsystem from the
other(s).
This register is implemented as write-once register. Once a value is written to it, the
value can be read back. Any subsequent writes will have no effect.
This register is not affected by the D3_HOT to D0 transition.
Bit
15:0
Subsystem Vendor ID — R/WO.
Description
Datasheet
691