BD82QM67-SLJ4M Datasheet, PDF (403/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Chipset Configuration Registers
10.1.40
PMSYNC_CFG—PMSYNC Configuration Register
Offset Address: 33C8–33CBh
Default Value: 00000000h
Attribute:
Size:
R/W
32-bit
Bit
31:12
11
10
9
8
7:0
Description
Reserved
GPIO_D Pin Selection (GPIO_D_SEL) — R/W. There are two possible GPIOs that
can be routed to the GPIO_D PMSYNC state. This bit selects between them:
0 = GPIO5 (default)
1 = GPIO0
GPIO_C Pin Selection (GPIO_C_SEL) — R/W. There are two possible GPIOs that
can be routed to the GPIO_C PMSYNC state. This bit selects between them:
0 = GPIO37 (default)
1 = GPIO4
GPIO_B Pin Selection (GPIO_B_SEL) — R/W. There are two possible GPIOs that
can be routed to the GPIO_B PMSYNC state. This bit selects between them:
0 = GPIO0 (default)
1 = GPIO37
GPIO_A Pin Selection (GPIO_A_SEL) — R/W. There are two possible GPIOs that
can be routed to the GPIO_A PMSYNC state. This bit selects between them:
0 = GPIO4 (default)
1 = GPIO5
Reserved
Datasheet
403