BD82QM67-SLJ4M Datasheet, PDF (90/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Signal Description
Table 2-27. Functional Strap Definitions (Sheet 2 of 4)
Signal
GNT1#/
GPIO51
Usage
Boot BIOS
Strap bit 1
BBS1
When
Sampled
Rising edge
of PWROK
Comment
This Signal has a weak internal pull-up.
Note that the internal pull-up is disabled after PLTRST#
deasserts.This field determines the destination of accesses to the
BIOS memory range. Also controllable using Boot BIOS Destination
bit (Chipset Config Registers: Offset 3410h:Bit 11). This strap is
used in conjunction with Boot BIOS Destination Selection 0 strap.
Bit11
0
1
1
0
Bit 10
1
0
1
0
Boot BIOS
Destination
Reserved
PCI
SPI
LPC
NOTES:
1. If option 00 (LPC) is selected, BIOS may still be placed on LPC,
but all platforms are required to have SPI flash connected
directly to the PCH's SPI bus with a valid descriptor in order to
boot.
2. Booting to PCI is intended for debut/testing only. Boot BIOS
Destination Select to LPC/PCI by functional strap or using Boot
BIOS Destination Bit will not affect SPI accesses initiated by
Intel^® ME or Integrated GbE LAN.
3. PCI Boot BIOS destination is not supported on Mobile
This Signal has a weak internal pull-up.
Note that the internal pull-up is disabled after PLTRST# deasserts.
This field determines the destination of accesses to the BIOS
memory range. Also controllable using Boot BIOS Destination bit
(Chipset Config Registers: Offset 3410h:Bit 10). This strap is used
in conjunction with Boot BIOS Destination Selection 1 strap.
SATA1GP/
GPIO19
GNT2#/
GPIO53
Boot BIOS
Strap bit 0
BBS0
ESI Strap
(Server/
Workstation
Only)
Rising edge
of PWROK
Rising edge
of PWROK
Bit11
0
1
1
0
Bit 10
1
0
1
0
Boot BIOS
Destination
Reserved
PCI
SPI
LPC
NOTES:
1. If option 00 (LPC) is selected, BIOS may still be placed on LPC,
but all platforms are required to have SPI flash connected
directly to the PCH's SPI bus with a valid descriptor in order to
boot.
2. Booting to PCI is intended for debut/testing only. Boot BIOS
Destination Select to LPC/PCI by functional strap or using Boot
BIOS Destination Bit will not affect SPI accesses initiated by
Management Engine or Integrated GbE LAN.
3. PCI Boot BIOS destination is not supported on mobile.
This Signal has a weak internal pull-up.
Tying this strap low configures DMI for ESI compatible operation.
NOTES:
1. The internal pull-up is disabled after PLTRST# deasserts.
2. ESI compatible mode is for server platforms only. This signal
should not be pulled low for desktop and mobile.
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Datasheet