BD82QM67-SLJ4M Datasheet, PDF (70/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Signal Description
Table 2-11. System Management Interface Signals (Sheet 2 of 2)
Name
SML1ALERT# /
PCHHOT# /
GPIO74
SML1CLK /
GPIO58
SML1DATA /
GPIO75
Type
Description
O OD
SMLink Alert 1: Alert for the ME SMBus controller to optional
Embedded Controller or BMC. External pull-up resistor is required.
This signal can instead be used as PCHHOT# or GPIO74
NOTE: A soft-strap determines the native function SML1ALERT# or
PCHHOT# usage. When soft-strap is 0, function is
SML1ALERT#, when soft-strap is 1, function is PCHHOT#.
I/OD
System Management Link 1 Clock: SMBus link to optional
Embedded Controller or BMC. External pull-up resistor is required.
This signal can instead be used as GPIO58
I/OD
System Management Link 1 Data: SMBus link to optional
Embedded Controller or BMC. External pull-up resistor is required.
This signal can instead be used as GPIO75
2.12 Real Time Clock Interface
Table 2-12. Real Time Clock Interface
Name
RTCX1
RTCX2
Type
Special
Special
Description
Crystal Input 1: This signal is connected to the 32.768 kHz crystal. If
no external crystal is used, then RTCX1 can be driven with the desired
clock rate.
Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If
no external crystal is used, then RTCX2 should be left floating.
2.13 Miscellaneous Signals
Table 2-13. Miscellaneous Signals (Sheet 1 of 2)
Name
INTVRMEN
DSWVRMEN
SPKR
Type
Description
Internal Voltage Regulator Enable: This signal enables the
internal 1.05 V regulators when pulled high.
This signal must be always pulled-up to VccRTC on desktop platforms
I _{and may optionally be pulled low on mobile platforms if using an}
external VR for the DcpSus rail.
NOTE: See VccCore signal description for behavior when INTVRMEN
is sampled low (external VR mode).
Deep S4/S5 Well Internal Voltage Regulator Enable: This signal
I ^{enables the internal DSW 1.05 V regulators.}
This signal must be always pulled-up to VccRTC.
Speaker: The SPKR signal is the output of counter 2 and is internally
“ANDed” with Port 61h Bit 1 to provide Speaker Data Enable. This
signal drives an external speaker driver device, which in turn drives
O ^{the system speaker. Upon PLTRST#, its output state is 0.}
NOTE: SPKR is sampled as a functional strap. See Section 2.27 for
more details. There is a weak integrated pull-down resistor on
SPKR pin.
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