BD82QM67-SLJ4M Datasheet, PDF (514/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

LPC Interface Bridge Registers (D31:F0)
13.8.1.4
GEN_PMCON_LOCK—General Power Management
Configuration Lock Register
Offset Address:
Default Value:
Lockable:
Power Well:
A6h
00h
No
Core
Attribute:
Size:
Usage:
RO, R/WLO
8-bit
ACPI
Bit
Description
7:3
Reserved
SLP Stretching Policy Lock-Down (SLP_STR_POL_LOCK) — R/WLO. When set
to 1, this bit locks down the Disable SLP Stretching After SUS Well Power Up,
SLP_S3# Minimum Assertion Width, SLP_S4# Minimum Assertion Width, SLP_S4#
Assertion Stretch Enable bits in the GEN_PMCON_3 register, making them read-
2
only.
This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit
are always ignored.
This bit is cleared by platform reset.
ACPI_BASE_LOCK — R/WLO. When set to 1, this bit locks down the ACPI Base
Address Register (ABASE) at offset 40h. The Base Address Field becomes read-
1
only.
This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit
are always ignored. Once locked by writing 1, the only way to clear this bit is to
perform a platform reset.
0
Reserved
13.8.1.5
CIR4—Chipset Initialization Register 4 (PM—D31:F0)
Offset Address:
Default Value:
Lockable:
Power Well:
A9h
03h
No
Core
Attribute:
Size:
Usage:
R/W
8-bit
ACPI, Legacy
Bit
Description
7:0 CIR4 Field 1 — R/W. BIOS must program this field to 47h.
13.8.1.6
BM_BREAK_EN_2 Register #2 (PM—D31:F0)
Offset Address:
Default Value:
Lockable:
Power Well:
AAh
00h
No
Core
Attribute:
Size:
Usage:
Bit
Description
7:1 Reserved
SATA3 Break Enable (SATA3_BREAK_EN) — R/W.
0 _{0 = SATA3 traffic will not cause BM_STS to be set.}
1 = SATA3 traffic will cause BM_STS to be set.
R/W, RO
8-bit
ACPI, Legacy
514
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