BD82QM67-SLJ4M Datasheet, PDF (875/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Intel® Management Engine Subsystem Registers (D22:F[3:0])
23.1.1.15
GMES—General Intel^® ME Status Register
(Intel^® MEI 1—D22:F0)
Address Offset: 48h–4Bh
Default Value: 00000000h
Attribute:
Size:
RO
32 bits
Bit
31:0
Description
General Intel ME Status (ME_GS)— RO. This field is populated by Intel ME.
23.1.1.16
H_GS—Host General Status Register
(Intel^® MEI 1—D22:F0)
Address Offset: 4Ch–4Fh
Default Value: 00000000h
Attribute:
Size:
RO
32 bits
Bit
31:0
Description
Host General Status(H_GS)— RO. General Status of Host, this field is not used by
Hardware
23.1.1.17
PID—PCI Power Management Capability ID Register
(Intel^® MEI 1—D22:F0)
Address Offset: 50h–51h
Default Value: 6001h
Attribute:
Size:
RO
16 bits
Bit
15:8
7:0
Description
Next Capability (NEXT) — RO. Value of 60h indicates the location of the next pointer.
Capability ID (CID) — RO. Indicates the linked list item is a PCI Power Management
Register.
23.1.1.18
PC—PCI Power Management Capabilities Register
(Intel^® MEI 1—D22:F0)
Address Offset: 52h–53h
Default Value: C803h
Attribute:
Size:
RO
16 bits
Bit
Description
15:11
PME_Support (PSUP) — RO. This five-bit field indicates the power states in which the
function may assert PME#. Intel MEI can assert PME# from any D-state except D1 or
D2 which are not supported by Intel MEI.
10:9 Reserved
8:6
Aux_Current (AC) — RO. Reports the maximum Suspend well current required when
in the D3_cold state. Value of 00b is reported.
5
Device Specific Initialization (DSI) — RO. Indicates whether device-specific
initialization is required.
4 Reserved
3 PME Clock (PMEC) — RO. Indicates that PCI clock is not required to generate PME#.
2:0
Version (VS) — RO. Hardwired to 011b to indicate support for Revision 1.2 of the PCI
Power Management Specification.
Datasheet
875