BD82QM67-SLJ4M Datasheet, PDF (852/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Thermal Sensor Registers (D31:F6)
22.1.15
SID—Subsystem ID Register
Address Offset: 2Eh–2Fh
Default Value: 0000h
Attribute:
Size:
R/WO
16 bits
This register should be implemented for any function that could be instantiated more
than once in a given system. The SID register, in combination with the Subsystem
Vendor ID register make it possible for the operating environment to distinguish one
subsystem from the other(s).
Software (BIOS) will write the value to this register. After that, the value can be read,
but writes to the register will have no effect. The write to this register should be
combined with the write to the SVID to create one 32-bit write. This register is not
affected by D3_HOT to D0 reset.
Bit
15:0
Description
SID (SAID) — R/WO. These R/WO bits have no PCH functionality.
22.1.16
CAP_PTR—Capabilities Pointer Register
Address Offset: 34h
Default Value: 50h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Capability Pointer (CP) — RO. Indicates that the first capability pointer offset is
offset 50h (Power Management Capability).
22.1.17
INTLN—Interrupt Line Register
Address Offset: 3Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0
Interrupt Line — R/W. PCH hardware does not use this field directly. It is used to
communicate to software the interrupt line that the interrupt pin is connected to.
22.1.18
INTPN—Interrupt Pin Register
Address Offset: 3Dh
Default Value: See description
Attribute:
Size:
RO
8 bits
Bit
Description
7:4 Reserved
3:0
Interrupt Pin — RO. This reflects the value of the Device 31 interrupt pin bits 27:24
(TTIP) in chipset configuration space.
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