BD82QM67-SLJ4M Datasheet, PDF (71/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Signal Description
Table 2-13. Miscellaneous Signals (Sheet 2 of 2)
Name
Type
Description
RTC Reset: When asserted, this signal resets register bits in the RTC
well.
RTCRST#
NOTES:
I
1.
Unless CMOS is being cleared (only to be done in the G3
power state), the RTCRST# input must always be high when
all other RTC power planes are on.
2.
In the case where the RTC battery is dead or missing on the
platform, the RTCRST# pin must rise before the RSMRST#
pin.
Secondary RTC Reset: This signal resets the manageability register
bits in the RTC well when the RTC battery is removed.
SRTCRST#
SML1ALERT#/
PCHHOT#/
GPIO74
INIT3_3V#
GPIO35 / NMI#
(Server /
Workstation
Only)
PCIECLKRQ2# /
GPIO20 / SMI#
(Server /
Workstation
Only)
NOTES:
I 1.
The SRTCRST# input must always be high when all other RTC
power planes are on.
2.
In the case where the RTC battery is dead or missing on the
platform, the SRTCRST# pin must rise before the RSMRST#
pin.
PCHHOT#: This signal is used to indicate a PCH temperature out of
bounds condition to an external EC, when PCH temperature is greater
than value programmed by BIOS. An external pull-up resistor is
OD ^{required on this signal.}
O
OD O
OD O
NOTE: A soft-strap determines the native function SML1ALERT# or
PCHHOT# usage. When soft-strap is 0, function is
SML1ALERT#, when soft-strap is 1, function is PCHHOT#.
Initialization 3.3 V: INIT3_3V# is asserted by the PCH for 16 PCI
clocks to reset the processor. This signal is intended for Firmware
Hub.
NMI#: This is an NMI event indication to an external controller (such
as a BMC) on server/workstation platforms.
When operating as NMI event indication pin function (enabled when
"NMI SMI Event Native GPIO Enable" soft strap [PCHSTRP9:bit 16] is
set to 1), the pin is OD (open drain).
SMI#: This is an SMI event indication to an external controller (such
as a BMC) on server/workstation platforms.
When operating as SMI event indication pin function (enabled when
"NMI SMI Event Native GPIO Enable" soft strap [PCHSTRP9:bit 16] is
set to 1), the pin is OD (open drain).
Datasheet
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