BD82QM67-SLJ4M Datasheet, PDF (442/934 Pages) Intel Corporation – Intel® 6 Series Chipset and Intel® 6 Series Chipset and

Gigabit LAN Configuration Registers
12.1.16
CAPP—Capabilities List Pointer Register
(Gigabit LAN—D25:F0)
Address Offset: 34h
Default Value: C8h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the
capabilities list is at C8h in configuration space.
12.1.17
INTR—Interrupt Information Register
(Gigabit LAN—D25:F0)
Address Offset: 3Ch–3Dh
Default Value: 0100h
Function Level Reset: No
Attribute:
Size:
R/W, RO
16 bits
Bit
15:8
7:0
Description
Interrupt Pin (IPIN) — RO. Indicates the interrupt pin driven by the GbE LAN
controller.
01h = The GbE LAN controller implements legacy interrupts on INTA.
Interrupt Line (ILINE) — R/W. Default = 00h. Software written value to indicate
which interrupt line (vector) the interrupt is connected to. No hardware action is taken
on this register.
12.1.18
MLMG—Maximum Latency/Minimum Grant Register
(Gigabit LAN—D25:F0)
Address Offset: 3Eh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Maximum Latency/Minimum Grant (MLMG) — RO. Not used. Hardwired to 00h.
12.1.19
CLIST1—Capabilities List Register 1
(Gigabit LAN—D25:F0)
Address Offset: C8h–C9h
Default Value: D001h
Attribute:
Size:
RO
16 bits
Bit
15:8
7:0
Description
Next Capability (NEXT) — RO. Value of D0h indicates the location of the next pointer.
Capability ID (CID) — RO. Indicates the linked list item is a PCI Power Management
Register.
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